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1997,1999 data sheet m pd784927, 784928, 784927y, 784928y description the m pd784927 and 784928 are members of the nec 78k/iv series of microcontrollers equipped with a high- speed, high-performance 16-bit cpu for vcr software servo control. the m pd784927y and 784928y are based on the m pd784928 with the addition of an i 2 c bus interface compatible with multi-master. they contain many peripheral hardware units ideal for vcr control, such as a multi-function timer unit (super timer unit) for software servo control and vcr analog circuits. flash memory models, the m pd78f4928 and m pd78f4928y, are under development. the functions of the m pd784927 is described in detail in the following users manual. be sure to read this manual before designing your system. m pd784928, 784928y subseries users manual - hardware : u12648e 78k/iv series users manual - instruction : u10905e features ? high instruction execution speed realized by 16-bit cpu core ? minimum instruction execution time: 250 ns (with 8 mhz internal clock) ? high internal memory capacity item part number m pd784927, 784927y m pd784928, 784928y internal rom capacity 96k bytes 128k bytes internal ram capacity 2048 bytes 3584 bytes ? vcr analog circuits conforming to vhs standard ? ctl amplifier ? dfg amplifier ? reel fg comparator (2 channels) ? recctl driver (rewritable) ? dpg amplifier ? csync comparator ? cfg amplifier ? dpfg separation circuit (ternary separation circuit) ? timer unit (super timer unit) for servo control ? serial interface : 3 channels ? 3-wire serial i/o : 2 channels ? i 2 c bus interface: 1 channel ? a/d converter: 12 channels (conversion time: 10 m s) ? low-frequency oscillation mode: main system clock frequency = internal clock frequency ? low-power consumption mode: cpu can operate with a subsystem clock. ? supply voltage range: v dd = +2.7 to 5.5 v ? hardware watch function: watch operation at low voltage (v dd = 2.7 v (min.)) and low current consumption unless otherwise specified, the m pd784927 is treated as the representative model throughout this document. 16-bit single-chip microcontroller mos integrated circuit the mark shows major revised points. document no. u12255ej2v0ds00 (2nd edition) date published december 1999 n cp(k) printed in japan the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
m pd784927, 784928, 784927y, 784928y 2 data sheet u12255ej2v0ds00 application fields stationary vcr, video camera, in-tv vcr ordering information (1) m pd784928 subseries part number package m pd784927gc- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd784927gf- -3ba 100-pin plastic qfp (14 20 mm) m pd784928gc- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd784928gf- -3ba 100-pin plastic qfp (14 20 mm) (2) m pd784928y subseries part number package m pd784927ygc- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd784927ygf- -3ba 100-pin plastic qfp (14 20 mm) m pd784928ygc- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd784928ygf- -3ba 100-pin plastic qfp (14 20 mm) note under development remark indicates rom code suffix. product development of vcr-servo microcontrollers the product development of vcr-servo microcontrollers is shown below. enclosed in a frame are subseries names. the y subseries is a collection of products supporting the i 2 c bus. products under mass production products under development 78k/iv series 78k/i series 100-pin qfp. with flash memory. expanded internal memory capacity. more powerful analog amplifier. improved vcr functions. increased i/o. high-current port added. i 2 c function added (y model only). 80-pin qfp pd784928 m pd784915 m pd78148 m pd78138 m pd784928y m 100-pin qfp expanded internal ram capacity. operational amplifier, watch function, multiplier added. 100-pin qfp. expanded internal memory capacity. internal analog amplifier. reinforced super timer. low-power consumption mode added.
3 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 m pd784927, 784927y m pd784928, 784928y 96k bytes 128k bytes 2048 bytes 3584 bytes 16 mhz (internal clock: 8 mhz) low frequency oscillation mode : 8 mhz (internal clock: 8 mhz) low power consumption mode : 32.768 khz (subsystem clock) 250 ns (with 8 mhz internal clock) 74 input : 20 i/o : 54 (including 8 ports for led direct drive) 11 (including one each for pseudo v sync , head amplifier switch, and chrominance rotation) timer/counter compare register capture register remark tm0 (16 bits) 3 tm1 (16 bits) 3 1 frc (22 bits) 6 tm3 (16 bits) 2 1 udc (5 bits) 1 ec (8 bits) 4 for hsw signal generation edv (8 bits) 1 for cfg signal division input signal number of bits measurable cycle operating edge cfg 22 125 ns to 524 ms - dfg 22 125 ns to 524 ms - hsw 16 1 m s to 65.5 ms - v sync 22 125 ns to 524 ms - ctl 16 1 m s to 65.5 ms - t reel 22 125 ns to 524 ms - s reel 22 125 ns to 524 ms - v sync separation circuit, h sync separation circuit viss detection, wide aspect detection circuits field identification circuit head amplifier switch/chrominance rotation output circuit timer compare register capture register tm2 (16 bits) 1 tm4 (16 bits) 1 (capture/compare) 1 tm5 (16 bits) 1 16-bit resolution : 3 channels (carrier frequency: 62.5 khz) 8-bit resolution : 3 channels (carrier frequency: 62.5 khz) 3-wire serial i/o: 2 channels (busy/strb control: 1 channel) i 2 c bus interface: 1 channel ( m pd784928y subseries only) 8-bit resolution 12 channels, conversion time: 10 m s function list (1/2) part number item internal rom capacity internal ram capacity operating clock minimum instruction execu- tion time i/o port real-time output port timer/counter capture register vcr special circuit general-purpose timer pwm output serial interface a/d converter super timer unit
m pd784927, 784928, 784927y, 784928y 4 data sheet u12255ej2v0ds00 function list (2/2) part number item analog circuit interrupt sources external internal standby function watch function buzzer output function supply voltage package m pd784927, 784927y m pd784928, 784928y ctl amplifier recctl driver (rewritable) dfg amplifier, dpg amplifier, cfg amplifier dpfg separation circuit (ternary separation circuit) reel fg comparator (2 channels) csync comparator 4 levels (programmable), vectored interrupt, macro service, context switching 9 (including nmi) 22 (including software interrupt) 23 (including software interrupt) halt mode/stop mode/low power consumption mode/low power consumption halt mode stop mode can be released by input of valid edge of nmi pin, watch interrupt (intw), or intp1/ intp2/key0-key4 pins 0.5-second measurement, low-voltage operation (v dd = 2.7 v) 1.95 khz, 3.91 khz, 7.81 khz, 15.6 khz (internal clock: 8 mhz) 2.048 khz, 4.096 khz, 32.768 khz (subsystem clock: 32.768 khz) v dd = +2.7 to 5.5 v ? 100-pin plastic lqfp (fine pitch)(14 14 mm) note ? 100-pin plastic qfp (14 20 mm) note under development
5 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 pin configuration (top view) 100-pin plastic lqfp (fine pitch)(14 14 mm) m pd784927gc- -8eu note 1 , 784928gc- -8eu note 1 m pd784928ygc- -8eu, 784928ygc- -8eu note 1 notes 1. under development 2. pins scl and sda are provided for the m pd784928y subseries only. caution directly connect the ic (internally connected) pins to v ss in the normal operation mode. p65/hwin/dpgmon p64/buz/dfgmon p103/csyncin p102/reel0in/intp3 p101/reel1in dfgin p100/dpgin cfgcpin cfgamp0 cfgin av dd1 av ss1 vrefc ctlout2 ctlout1 ctlin recctl - recctl + ctldly av ss2 p113/ani11 p112/ani10 p111/ani9 p110/ani8 p77/ani7 p84/pwm2/sda note 2 p83/rotc p82/hasw p80 p57 p56 p55 p54 p53 p52 p51 p50 v ss v dd p47 p46 p45 p44 p43 p42 p41 p40 p07 p06 p05 p04 p03 p02 p01 p00 p23/intp2 p22/intp1 p21/intp0 p20/nmi p90/env p91/key0 p92/key1 p93/key2 p94/key3 p95/key4 p96 av dd2 av ref p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p85/pwm3/scl note 2 p86/pto10 p87/pto11 p30/pto00 p31/pto01 p32/pto02 ic reset x1 x2 v ss xt2 xt1 v dd p33/si2/busy p34/so2 p35/sck2 p36/pwm1 p37/pwm0 p63/si1 p62/so1 p61/sck1/buz p60/strb/clo p67/pwm5/ctlmon p66/pwm4/cfgmon 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 80 79 78 77 76 46 47 48 49 50
m pd784927, 784928, 784927y, 784928y 6 data sheet u12255ej2v0ds00 100-pin plastic qfp (14 20 mm) m pd784927gf- -3ba, 784928gf- -3ba, m pd784927ygf- -3ba, 784928ygf- -3ba note pins scl and sda are provided for the m pd784928y subseries only. caution directly connect the ic (internally connected) pins to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dfgmon/p64/buz dpgmon/p65/hwin cfgmon/p66/pwm4 ctlmon/p67/pwm5 p60/strb/clo p61/sck1/buz p62/so1 p63/si1 p37/pwm0 p36/pwm1 p35/sck2 p34/so2 p33/si2/busy v dd xt1 xt2 v ss x2 x1 reset ic p32/pto02 p31/pto01 p30/pto00 p87/pto11 p86/pto10 scl note /p85/pwm3 sda note /p84/pwm2 p83/rotc p82/hasw 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ani9/p111 ani8/p110 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 av ref av dd2 p96 p95/key4 p94/key3 p93/key2 p92/key1 p91/key0 p90/env nmi/p20 intp0/p21 intp1/p22 intp2/23 p00 p01 p02 p03 p04 p05 p06 100 csyncin/p103 99 reel0in/intp3/p102 98 reel1in/p101 97 dfgin 96 dpgin/p100 95 cfgcpin 94 cfgampo 93 cfgin 92 av dd1 91 av ss1 90 vrefc 89 ctlout2 88 ctlout1 87 ctlin 86 recctl - 85 recctl+ 84 ctldly 83 av ss2 82 ani11/p113 81 ani10/p112 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p80 p57 p56 p55 p54 p53 p52 p51 p50 v ss v dd p47 p46 p45 p44 p43 p42 p41 p40 p07
7 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 ani0-ani11 : analog input av dd1 , av dd2 : analog power supply av ss1 , av ss2 : analog ground av ref : analog reference voltage busy : serial busy buz : buzzer output cfgampo : capstan fg amplifier output cfgcpin : capstan fg capacitor input cfgin : analog unit input cfgmon : capstan fg monitor clo : clock output csyncin : analog unit input ctldly : control delay input ctlin : ctl amplifier input capacitor ctlmon : ctl amplifier monitor ctlout1, ctlout2 : ctl amplifier output dfgin : analog unit input dfgmon : dfg monitor dpgin : analog unit input dpgmon : dpg monitor env : envelope input hasw : head amplifier switch output hwin : hardware timer external input ic : internally connected intp0-intp3 : interrupt from peripherals key0-key4 : key return nmi : nonmaskable interrupt p00-p07 : port0 p20-p23 : port2 p30-p37 : port3 p40-p47 : port4 p50-p57 : port5 p60-p67 : port6 p70-p77 : port7 p80, p82-p87 : port8 p90-p96 : port9 p100-p103 : port10 p110-p113 : port11 pto00-pto02, pto10, pto11 : programmable timer output pwm0-pwm5 : pulse width modulation output recctl+, recctlC : recctl output/pbclt input reel0in, reel1in : analog unit input reset : reset rotc : chrominance rotate output sck1, sck2 : serial clock scl note : serial clock sda note : serial data si1, si2 : serial input so1, so2 : serial output strb : serial strobe v dd : power supply vrefc : reference amplifier capacitor v ss : ground x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) note pins scl and sda are provided for the m pd784928y subseries only.
m pd784927, 784928, 784927y, 784928y 8 data sheet u12255ej2v0ds00 internal block diagram note only the m pd784928 subseries supports i 2 c bus interface. remark internal rom and ram capacities differ depending on the product. vrefc reel0in reel1in csyncin dfgin dpgin cfgin cfgampo cfgcpin ctlout1 ctlout2 ctlin recctl+ recctl - ctldly an10-an11 av dd1 , av dd2 av ss1 , av ss2 av ref nmi intp0-intp3 pwm0-pwm5 pto00-pto02 pto10, pto11 interrupt control super timer unit analog unit & a/d converter serial interface 1 serial interface 2 serial interface 3 note si1 so1 sck1 si2/busy so2 sck2 strb sda scl 78k/iv 16-bit cpu core (ram: 512 bytes) ram system control clock output clo buzzer output buz key input key0-key4 p00-p07 p80, p82, p83 real-time output port port0 p00-p07 port4 p40-p47 port5 p50-p57 port6 p60-p67 port7 p70-p77 port8 p80, p82-p87 port9 p90-p96 v dd v ss x1 x2 xt1 xt2 reset port2 p20-p23 port3 p30-p37 port10 p100-p103 port11 p110-p113 dfgmon dpgmon cfgmon ctlmon rom
9 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 system configuration example ? video camera note pins scl and sda are provided for the m pd784928y subseries only. drum motor m driver capstan motor m driver loading motor m driver ctl head audio/video signal processing circuit composite sync signal video head switch audio head switch pseudo vertical sync signal remote controller signal remote controller reception signal m pc2800a m pd784927 dfgin dpgin pwm0 dfg dpg cfg cfgin pwm1 recctl+ recctl - pwm2 port csyncin pto00 pto01 p80 intp2 port port port sck1 si1 so1 intp0 port sck2 so2 busy port strb port +v dd key matrix intp0 sck so si port camera- controlling microcontroller pd784038 m camera block cs clk data busy lcd c/d pd7225 m lcd display panel cs clk data busy stb osd pd6461 m mechanical block eeprom tm 16 mhz 32.768 khz xt1 xt2 x1 x2 other ics +v dd sda scl sda note scl note sda scl
m pd784927, 784928, 784927y, 784928y 10 data sheet u12255ej2v0ds00 ? stationary vcr note pins scl and sda are provided for the m pd784928y subseries only. drum motor m driver capstan motor m driver loading motor m driver ctl head dfgin dpgin pwm0 dfg dpg cfg cfgin pwm1 recctl+ recctl - pwm2 m pd784927 reel motor m driver reel fg0 reel0in pwm3 m driver pwm4 reel fg1 reel1in cs clk data osd pd6464a m fip key matrix composite sync signal video head switch audio head switch pseudo vertical sync signal audio/video signal processing circuit tuner mechanical block m pc2800a remote controller signal remote controller reception signal stb clk dout din fip tm c/d pd16311 m port sck1 si1 so1 port sck2 so2 port csyncin pto00 pto01 p80 pwm5 port port intp2 8 mhz 32.768 khz xt1 xt2 x1 x2 low frequency oscillation mode +v dd eeprom other ics +v dd sda scl sda note scl note sda scl
11 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 contents 1. difference between m pd784928 subseries and 784928y subseries .................... 12 2. pin function ............................................................................................................................... 13 2.1 port pins ............................................................................................................................... ................. 13 2.2 pins other than port pins .................................................................................................................. 14 2.3 i/o circuits of pins and processing of unused pins ...................................................................... 16 3. internal block function ..................................................................................................... 19 3.1 cpu registers ............................................................................................................................... ....... 19 3.1.1 general-purpose registers ......................................................................................................... 19 3.1.2 other cpu registers ................................................................................................................... 20 3.2 memory space ............................................................................................................................... ....... 21 3.3 special function registers (sfrs) ................................................................................................... 24 3.4 ports ............................................................................................................................... ........................ 30 3.5 real-time output port ......................................................................................................................... 31 3.6 super timer unit ............................................................................................................................... ... 35 3.7 serial interface ............................................................................................................................... ...... 41 3.8 a/d converter ............................................................................................................................... ........ 44 3.9 vcr analog circuits ............................................................................................................................ 45 3.10 watch function ............................................................................................................................... ..... 50 3.11 clock output function ........................................................................................................................ 51 3.12 buzzer output function ...................................................................................................................... 52 4. internal/external control function ........................................................................... 53 4.1 interrupt function ............................................................................................................................... .53 4.1.1 vectored interrupt ....................................................................................................................... 56 4.1.2 context switching ....................................................................................................................... 56 4.1.3 macro service ............................................................................................................................. 57 4.1.4 application example of macro service ...................................................................................... 59 4.2 standby function ............................................................................................................................... .. 62 4.3 clock generation circuit ..................................................................................................................... 64 4.4 reset function ............................................................................................................................... ...... 65 5. instruction set ........................................................................................................................ 66 6. electrical specifications .................................................................................................. 70 7. package drawing .................................................................................................................... 85 8. recommended soldering conditions ............................................................................. 87 appendix a. development tools ............................................................................................ 88 appendix b. related documents ............................................................................................ 91
m pd784927, 784928, 784927y, 784928y 12 data sheet u12255ej2v0ds00 1. difference between m pd784928 subseries and 784928y subseries the m pd78f4928 and 78f4928y are based on the m pd784927 and 784927y and are provided with a 128k-byte flash memory instead of a mask rom. table 1-1 shows the differences between the products in the m pd784928 subseries and 784928y subseries. table 1-1. differences between m pd784928 subseries and 784928y subseries part number m pd784927, m pd784928, m pd78f4928, item m pd784927y m pd784928y m pd78f4928y internal rom mask rom flash memory 96k bytes 128k bytes internal ram 2048 bytes 3584 bytes internal memory capacity not provided provided select register (ims) ic pin provided not provided v pp pin not provided provided electrical characteristics refer to the data sheet of each product.
13 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 2. pin function 2.1 port pins pin name i/o shared with: function p00-p07 i/o real-time 8-bit i/o port (port 0). output port can be set in input or output mode in 1-bit units. can be connected with software pull-up resistors. p20 input nmi 4-bit i/o port (port 2). p21-p23 intp0-intp2 can be connected with software pull-up resistors (p22 and p23 only). p30-p32 i/o pto00-pto02 8-bit i/o port (port 3). p33 si2/busy can be set in input or output mode in 1-bit units. p34 so2 can be connected with software pull-up resistors. p35 sck2 p36, p37 pwm1, pwm0 p40-p47 i/o 8-bit i/o port (port 4). can be set in input or output mode in 1-bit units. can be connected with software pull-up resistors. can directly drive led. p50-p57 i/o 8-bit i/o port (port 5). can be set in input or output mode in 1-bit units. can be connected with software pull-up resistors. p60 i/o strb/clo 8-bit i/o port (port 6). p61 sck1/buz can be set in input or output mode in 1-bit units. p62 so1 can be connected with software pull-up resistors. p63 si1 p64 dfgmon/buz p65 dpgmon/hwin p66 cfgmon/pwm4 p67 ctlmon/pwm5 p70-p77 input ani0-ani7 8-bit input port (port 7) p80 i/o real-time pseudo v sync output 7-bit i/o port (port 8). p82 output port hasw output can be set in input or output mode p83 rotc output in 1-bit units. p84 pwm2/sda note can be connected with software p85 pwm3/scl note pull-up resistors. p86 pto10 p87 pto11 p90 i/o env 7-bit i/o port (port 9). p91-p95 key0-key4 can be set in input or output mode in 1-bit units. p96 can be connected with software pull-up resistors. p100 input dpgin 4-bit input port (port 10). p101 reel1in p102 reel0in/intp3 p103 csyncin p110-p113 input ani8-ani11 4-bit input port (port 11). note pins scl and sda are provided for the m pd784928y subseries only.
m pd784927, 784928, 784927y, 784928y 14 data sheet u12255ej2v0ds00 2.2 pins other than port pins (1/2) pin name i/o shared with: function reel0in input p102/intp3 reel fg input reel1in p101 dfgin drum fg, pfg input (ternary) dpgin p100 drum pg input cfgin capstan fg input csyncin p103 composite sync input cfgcpin cfg comparator input cfgampo output cfg amplifier output pto00 output p30 programmable timer output of super timer unit pto01 p31 pto02 p32 pto10 p86 pto11 p87 pwm0 output p37 pwm output of super timer unit pwm1 p36 pwm2 p84/sda note pwm3 p85/scl note pwm4 p66/cfgmon pwm5 p67/ctlmon hasw output p82 head amplifier switch signal output rotc output p83 chrominance rotation signal output env input p90 envelope signal input si1 input p63 serial data input (serial interface channel 1) so1 output p62 serial data output (serial interface channel 1) sck1 i/o p61/buz serial clock i/o (serial interface channel 1) si2 input p33/busy serial data input (serial interface channel 2) so2 output p34 serial data output (serial interface channel 2) sck2 i/o p35 serial clock i/o (serial interface channel 2) busy input p33/si2 serial busy signal input (serial interface channel 2) strb output p60/clo serial strobe signal output (serial interface channel 2) sda i/o p84/pwm2 i 2 c bus data i/o scl i/o p85/pwm3 i 2 c bus clock i/o ani0-ani7 analog input p70-p77 analog signal input of a/d converter ani8-ani11 p110-p113 ctlin ctl amplifier input capacitor connection ctlout1 output ctl amplifier output ctlout2 i/o logic signal input/ctl amplifier output recctl+, recctlC i/o recctl signal output/pbctl signal input ctldly external time constant connection (for recctl rewriting) note pins scl and sda are provided for the m pd784928y subseries only.
15 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 2.2 pins other than port pins (2/2) pin name i/o shared with: function vrefc vref amplifier ac connection dfgmon output p64/buz drum fg signal output dpgmon p65/hwin drum pg signal output cfgmon p66/pwm4 cfg signal output ctlmon p67/pwm5 ctl signal output nmi input p20 non-maskable interrupt request input intp0-intp2 input p21-p23 external interrupt request input intp3 input p102/reel0in key0-key4 input p91-p95 key input signal input clo output p60/strb clock output buz output p61/sck1 buzzer output p64/dfgmon hwin input p65/dpgmon external input of hardware watch counter reset input reset input x1 input crystal connection for main system clock oscillation x2 xt1 input crystal connection for subsystem clock oscillation. xt2 crystal connection for watch clock oscillation av dd1 positive power supply to analog amplifier circuit av dd2 positive power supply to a/d converter and analog circuits input buffer av ss1 gnd of analog amplifier circuit av ss2 gnd of a/d converter and analog circuits input buffer av ref reference voltage input to a/d converter v dd positive power supply to digital circuits v ss gnd of digital circuits ic internally connected. directly connect this pin to v ss .
m pd784927, 784928, 784927y, 784928y 16 data sheet u12255ej2v0ds00 2.3 i/o circuits of pins and processing of unused pins table 2-1 shows the types of the i/o circuits of the respective pins and processing of the unused pins. figure 2-1 shows the circuits of the respective types. table 2-1. i/o circuits of respective pins and processing of unused pins (1/2) pin i/o circuit type i/o recommended connection of unused pins p00-p07 5-a i/o input: connect to v dd . output: leave unconnected. p20/nmi 2 input connect to v dd . p21/intp0 connect to v dd or v ss . p22/intp1, p23/intp2 2-a connect to v dd . p30/pto00-p32/pto02 5-a i/o input: connect to v dd . p33/si2/busy 8-a output: leave unconnected. p34/so2 5-a p35/sck2 8-a p36/pwm1, p37/pwm0 5-a p40-p47 p50-p57 p60/strb/clo p61/sck1/buz 8-a p62/so1 5-a p63/si1 8-a p64/dfgmon/buz 5-a p65/hwin/dpgmon 8-a p66/pwm4/cfgmon 5-a p67/pwm5/ctlmon p70/ani0-p77/ani7 9 input connect to v ss . p80 5-a i/o input: connect to v dd . p82/hasw output: leave unconnected. p83/rotc p84/pwm2/sda note 10-a p85/pwm3/scl note p86/pto10 5-a p87/pto11 p90/env p91/key0-p95/key4 8-a p96 5-a note pins scl and sda are provided for the m pd784928y subseries only.
17 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 table 2-1. i/o circuits of respective pins and processing of unused pins (2/2) pin i/o circuit type i/o recommended connection of unused pins p100/dpgin input when endrum = 0 or endrum = 1 and selpgsepa = 0: connect to v ss . p101/reel1in when enreel = 0: connect to v ss . p102/reel0in/intp3 p103/csyncin when encsyn = 0: connect to v ss . p110/ani8-p113/ani11 9 input connect to v ss . recctl+, recctlC i/o when enctl = 0 and enrec = 0: connect to v ss . dfgin input when endrum = 0: connect to v ss . cfgin, cfgcpin when encap = 0: connect to v ss . ctlout1 output leave unconnected. ctlout2 i/o when enctl = 0 and encomp = 0: connect to v ss . when enctl = 1: leave unconnected. cfgampo output leave unconnected. ctlin when enctl = 0: leave unconnected. vrefc when enctl = 0 and encap = 0 and encomp = 0: leave unconnected. ctldly leave unconnected. av dd1 , av dd2 connect to v dd . av ref , av ss1 , av ss2 connect to v ss . reset 2 xt1 connect to v ss . xt2 leave unconnected. ic directly connect to v ss . remark enctl : bit 1 of amplifier control register (ampc) enrec : bit 7 of amplifier mode register 0 (ampm0) endrum : bit 2 of amplifier control register (ampc) selpgsepa : bit 2 of amplifier mode register 0 (ampm0) encap : bit 3 of amplifier control register (ampc) encsyn : bit 5 of amplifier control register (ampc) enreel : bit 6 of amplifier control register (ampc) encomp : bit 4 of amplifier control register (ampc)
m pd784927, 784928, 784927y, 784928y 18 data sheet u12255ej2v0ds00 figure 2-1. i/o circuits of respective pins in p-ch v dd pull-up enable in type 2 type 2-a schmitt trigger input with hysteresis characteristics schmitt trigger input with hysteresis characteristics type 5-a type 8-a p-ch n-ch v dd in/ out output disable data input enable pull-up enable p-ch type 9 type 10-a v dd p-ch n-ch v dd in/ out output disable data pull-up enable p-ch v dd p-ch n-ch in comparator v ref (threshold voltage) + - input enable v dd p-ch n-ch p-ch v dd in/out pull-up enable data open drain output disable
19 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 3. internal block function 3.1 cpu registers 3.1.1 general-purpose registers the m pd784927 has eight banks of general-purpose registers. one bank consists of sixteen 8-bit general-purpose registers. two of these 8-bit registers can be used in pairs as a 16-bit register. four of the 16-bit general-purpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register. these eight banks of general-purpose registers can be selected by software or context switching function. the general-purpose registers, except for the address expansion registers v, u, t, and w, are mapped to the internal ram. figure 3-1. configuration of general-purpose register caution although r4, r5, r6, r7, rp2, and rp3 can be used as x, a, c, b, ax, and bc registers, respectively, by setting the rss bit of psw to 1, do not use this function. the function of the rss bit is planned to be deleted from the future models in the 78k/iv series. 8 banks ( ): absolute name a (r1) x (r0) b (r3) c (r2) r5 r4 r7 r6 r9 r8 v r11 r10 u d (r13) e (r12) t h (r15) l (r14) w ax (rp0) bc (rp1) rp2 rp3 vp (rp4) vvp (rg4) up (rp5) uup (rg5) de (rp6) tde (rg6) hl (rp7) whl (rg7)
m pd784927, 784928, 784927y, 784928y 20 data sheet u12255ej2v0ds00 3.1.2 other cpu registers (1) program counter the program counter of the m pd784927 is 20 bits wide. the value of the program counter is automatically updated as the program is executed. (2) program status word this is a register that holds the various statuses of the cpu. its contents are automatically updated as the program is executed. note the rss flag is provided to maintain compatibility with the microcomputers in the 78k/iii series. always clear this flag to 0 except when the software of the 78k/iii series is used. (3) stack pointer this is a 24-bit pointer that holds the first address of the stack. be sure to write 0 to the high-order 4 bits. 19 0 pc pswh uf 15 rbs2 14 rbs1 13 rbs0 12 11 10 9 8 pswl s 7 z 6 rss 5 ac 4 ie 3 p/v 2 0 1 cy 0 note psw 23 0 000 20 0 sp
21 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 3.2 memory space a memory space of 1m bytes can be accessed. the mapping of the internal data area (special function registers and internal ram) can be selected by using the location instruction. the location instruction must be always executed after reset has been cleared, and cannot be used more than once. (1) when location 0h instruction is executed part number internal data area internal rom area m pd784927, 784927y 0f700h-0ffffh 00000h-0f6ffh 10000h-17fffh m pd784928, 784928y 0f100h-0ffffh 00000h-0f0ffh 10000h-1ffffh remark the area of the internal rom overlapping the internal data area cannot be used when the location 0 instruction is executed. part number unusable area m pd784927, 784927y 0f700h-0ffffh (2304 bytes) m pd784928, 784928y 0f100h-0ffffh (3840 bytes) (2) when location 0fh instruction is executed part number internal data area internal rom area m pd784927, 784927y ff700h-fffffh 00000h-17fffh m pd784928, 784928y ff100h-fffffh 00000h-1ffffh
m pd784927, 784928, 784927y, 784928y 22 data sheet u12255ej2v0ds00 figure 3-2. memory map of m pd784927, 784927y notes 1. accessed in external memory expansion mode 2. the 2304 bytes in this area can be used as an internal rom only when the location 0fh instruction is executed. 3. when location 0h instruction is executed: 96000 bytes, when location 0fh instruction is executed: 98304 bytes 4. base area or entry area for reset or interrupt. excluding the internal ram for reset. (256 bytes) special function registers (sfrs) internal rom (63232 bytes) internal ram (2048 bytes) cannot be used general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (1536 bytes) note 2 callf entry area (2k bytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (2048 bytes) cannot be used internal rom (96k bytes) note 4 when location 0h instruction is executed note 1 when location 0fh instruction is executed internal rom (32768 bytes) fffffh 18000h 17fffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 0f700h 0f6ffh 00000h 0feffh 0fe80h 0fe7fh 0fe3bh 0fe06h 0fd00h 0fcffh 0f700h 17fffh 10000h 0f6ffh 01000h 00800h 007ffh 00080h 0007fh 00040h 0003fh 00000h 00000h 17fffh 18000h fffffh fffdfh fffd0h fff00h ffeffh ff6ffh ff700h ffeffh ffe80h ffe7fh ffe3bh ffe06h ffd00h ffcffh ff700h 17fffh special function registers (sfrs) (256 bytes) note 4 note 1 00fffh
23 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 figure 3-3. memory map of m pd784928, 784928y notes 1. accessed in external memory expansion mode 2. the 3840 bytes in this area can be used as an internal rom only when the location 0fh instruction is executed. 3. when location 0h instruction is executed: 127232 bytes, when location 0fh instruction is executed: 131072 bytes 4. base area or entry area for reset or interrupt. excluding the internal ram for reset. (256 bytes) special function registers (sfrs) internal rom (61696 bytes) internal ram (3584 bytes) cannot be used general-purpose registers (128 bytes) macro service control word area (54 bytes) data area (512 bytes) program/data area (3072 bytes) note 2 callf entry area (2k bytes) program/data area note 3 callt table area (64 bytes) vector table area (64 bytes) internal ram (3584 bytes) cannot be used internal rom (128k bytes) note 4 when location 0h instruction is executed note 1 when location 0fh instruction is executed internal rom (65536 bytes) fffffh 20000h 1ffffh 10000h 0ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 0f100h 0f0ffh 00000h 0feffh 0fe80h 0fe7fh 0fe3bh 0fe06h 0fd00h 0fcffh 0f100h 1ffffh 10000h 0f0ffh 01000h 00800h 007ffh 00080h 0007fh 00040h 0003fh 00000h 00000h 1ffffh 20000h fffffh fffdfh fffd0h fff00h ffeffh ff0ffh ff100h ffeffh ffe80h ffe7fh ffe3bh ffe06h ffd00h ffcffh ff100h 1ffffh special function registers (sfrs) (256 bytes) note 4 note 1 00fffh
m pd784927, 784928, 784927y, 784928y 24 data sheet u12255ej2v0ds00 3.3 special function registers (sfrs) special function registers are assigned special functions and mapped to a 256-byte space of addresses ff00h through ffffh. these registers include mode registers and control registers that control the internal peripheral hardware units. caution do not access an address to which no sfr is assigned. if such an address is accessed by mistake, the m pd784927 may be deadlocked. this deadlock can be cleared only by reset input. table 3-1 lists the special function registers (sfrs). the meanings of the symbols in this table are as follows: symbol .................................... abbreviation of an sfr. this abbreviation is reserved for necs assembler (ra78k4). with a c compiler (cc78k4), the abbreviation can be used as sfr variable by the #pragma sfr instruction. r/w ......................................... indicates whether the sfr in question can be read or written. r/w : read/write r : read only w : write only bit length ................................. indicates the bit length (word length) of the sfr. bit units for manipulation ....... indicates bit units in which the sfr in question can be manipulated. an sfr that can be manipulated in 16-bit units can be used as the operand sfrp of an instruction. specify an even address to manipulate this sfr. an sfr that can be manipulated in 1-bit units can be used for a bit manipulation instruction. after clearing reset ................. indicates the status of each register immediately after clearing reset. caution the addresses shown in table 3-1 are used when the location 0h instruction is executed. add f0000h to the address values shown in the table when the location 0fh instruction is executed.
25 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 table 3-1. special function registers (1/5) address special function register (sfr) name symbol r/w bit bit units for manipulation after clearing length 1 bit 8 bits 16 bits reset ff00h port 0 p0 r/w 8 undefined ff02h port 2 p2 r 8 ff03h port 3 p3 r/w 8 ff04h port 4 p4 8 ff05h port 5 p5 8 ff06h port 6 p6 8 ff07h port 7 p7 r 8 ff08h port 8 p8 r/w 8 ff09h port 9 p9 8 ff0ah port 10 p10 r 8 ff0bh port 11 p11 8 ff0eh port 0 buffer register l p0l r/w 8 ff0fh port 0 buffer register h p0h 8 ff10h timer 0 compare register 0 cr00 16 cleared to 0 ff11h event counter compare register 0 ecc0 w 8 ff12h timer 0 compare register 1 cr01 r/w 16 ff13h event counter compare register 1 ecc1 w 8 ff14h timer 0 compare register 2 cr02 r/w 16 ff15h event counter compare register 2 ecc2 w 8 ff16h timer 1 compare register 0 cr10 r/w 16 ff17h event counter compare register 3 ecc3 w 8 ff18h timer 1 compare register 1 cr11 r/w 16 ff1ah timer 1 compare register 2 cr12 r 16 ff1ch timer 1 compare register 3 cr13 r/w 16 ff1eh timer 2 compare register 0 cr20 16 ff20h port 0 mode register pm0 8 ffh ff23h port 3 mode register pm3 8 ff24h port 4 mode register pm4 8 ff25h port 5 mode register pm5 8 ff26h port 6 mode register pm6 8 ff28h port 8 mode register pm8 8 fdh ff29h port 9 mode register pm9 8 7fh ff2eh real-time output port 0 control register rtpc 8 00h ff30h timer counter 0 tm0 r 16 cleared to 0 ff31h event counter ec r/w 8 ff32h timer counter 1 tm1 r 16 ff34h free running counter (bits 0-15) frcl 16 0000h ff35h free running counter (bits 16-21) frch 8 00h ff36h timer counter 2 tm2 16 cleared to 0 remark cleared to 0: counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
m pd784927, 784928, 784927y, 784928y 26 data sheet u12255ej2v0ds00 table 3-1. special function registers (2/5) address special function register (sfr) name symbol r/w bit bit units for manipulation after clearing length 1 bit 8 bits 16 bits reset ff38h timer control register 0 tmc0 r/w 8 00h ff39h timer control register 1 tmc1 8 ff3ah timer control register 2 tmc2 8 ff3bh timer control register 3 tmc3 8 00 00000 ff3ch timer counter 3 tm3 r 16 cleared to 0 ff3dh timer control register 4 tmc4 r/w 8 000000 ff3eh timer counter 4 tm4 r 16 cleared to 0 ff43h port 3 mode control register pmc3 r/w 8 00h ff48h port 8 mode control register pmc8 8 ff4bh control mode select register cms 8 ff4dh trigger source select register 0 trgs0 8 ff4eh pull-up resistor option register l puol 8 ff4fh pull-up resistor option register h puoh 8 ff50h input control register icr 8 10h ff51h up/down counter count register udc 8 undefined ff52h event divider counter edv r 8 cleared to 0 ff53h capture mode register cptm r/w 8 00h ff54h timer counter 5 tm5 r 16 cleared to 0 ff56h timer 3 capture register 0 cpt30 16 ff58h timer 0 output mode register tom0 w 8 000000 ff59h timer 0 output control register toc0 8 00h ff5ah timer 1 output mode register tom1 note 1 r/w 8 80h ff5bh timer 1 output control register toc1 w 8 00h ff5ch timer 3 compare register 0 cr30 r/w 16 cleared to 0 ff5eh timer 3 compare register 1 cr31 16 ff60h port 8 buffer register l p8l 8 000 0 0 ff63h up/down counter compare register udcc w 8 undefined ff65h trigger source select register 1 trgs1 r/w 8 00h ff66h port 6 mode control register pmc6 8 ff68h a/d converter mode register adm 16 0000h adml note 2 8 ff6ah a/d conversion result register adcr r 8 undefined ff6ch hardware watch counter 0 hw0 r/w 16 not affected ff6eh hardware watch counter 1 hw1 r 16 by reset ff6fh watch mode register wm r/w 8 00 0 00 ff70h pwm control register 0 pwmc0 8 05h notes 1. when the tom1 is read, the write sequence of the rec driver is read (bits 0 and 1). 2. adml is the low-order 8 bits of adm and can be manipulated in 1- or 8-bit units. remark cleared to 0: counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
27 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 table 3-1. special function registers (3/5) address special function register (sfr) name symbol r/w bit bit units for manipulation after clearing length 1 bit 8 bits 16 bits reset ff71h pwm control register 1 pwmc1 r/w 8 15h ff72h pwm0 modulo register pwm0 16 0000h ff73h pwm2 modulo register pwm2 8 00h ff74h pwm1 modulo register pwm1 16 0000h ff75h pwm3 modulo register pwm3 8 00h ff76h pwm5 modulo register pwm5 16 0000h ff77h pwm4 modulo register pwm4 8 00h ff78h event divider control register edvc w 8 cleared to 0 ff79h clock output mode register clom r/w 8 00h ff7ah timer 4 capture/compare register 0 cr40 16 cleared to 0 ff7bh clock control register cc 8 00h ff7ch timer 4 capture register 1 cr41 r 16 cleared to 0 ff7dh capture/compare control register crc w 8 00h ff7eh timer 5 compare register cr50 r/w 16 cleared to 0 ff80h i 2 c control register iicc 8 00h ff82h i 2 c clock select register iiccl 8 ff84h serial mode register 1 csim1 8 ff85h serial shift register 1 sio1 8 undefined ff86h slave address register sva 8 00h ff88h serial mode register 2 csim2 8 ff89h serial shift register 2 sio2 8 undefined ff8ah serial control register 2 csic2 8 00h ff8ch i 2 c bus status register note iics r 8 ff8eh i 2 c bus shift register note iic r/w 8 ff90h amplifier mode register 2 ampm2 8 ff91h head amplifier switch output control register hapc 8 ff94h amplifier control register ampc 8 ff95h amplifier mode register 0 ampm0 8 ff96h amplifier mode register 1 ampm1 8 ff97h gain control register ctlm 8 ff98h viss detection circuit shift register 0 vsft0 16 0000h ff99h ff9ah viss detection circuit shift register 1 vsft1 16 ff9bh ffa0h external interrupt mode register intm0 8 000000 0 ffa1h external capture mode register 1 intm1 8 00h ffa2h external capture mode register 2 intm2 8 ffa3h viss detection circuit control register vdc 8 note these registers are provided for the m pd784928y subseries only. remark cleared to 0: counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
m pd784927, 784928, 784927y, 784928y 28 data sheet u12255ej2v0ds00 table 3-1. special function registers (4/5) address special function register (sfr) name symbol r/w bit bit units for manipulation after clearing length 1 bit 8 bits 16 bits reset ffa4h viss detection circuit up/down counter register vudc r/w 8 00h ffa5h vudc value setting register vudst 8 ffa6h key interrupt control register keyc 8 70h ffa7h viss pulse pattern setting register vps 8 00h ffa8h in-service priority register ispr r 8 ffaah interrupt mode control register imc r/w 8 80h ffach interrupt mask flag register mk0l mk0 8 ffh ffadh mk0h 8 ffaeh mk1l mk1 8 ffafh mk1h 8 ffb0h frc capture register 0l cpt0l r 16 cleared to 0 ffb1h frc capture register 0h cpt0h 8 ffb2h frc capture register 1l cpt1l 16 ffb3h frc capture register 1h cpt1h 8 ffb4h frc capture register 2l cpt2l 16 ffb5h frc capture register 2h cpt2h 8 ffb6h frc capture register 3l cpt3l 16 ffb7h frc capture register 3h cpt3h 8 ffb8h frc capture register 4l cpt4l 16 ffb9h frc capture register 4h cpt4h 8 ffbah frc capture register 5l cpt5l 16 ffbbh frc capture register 5h cpt5h 8 ffbdh v sync separation circuit control register vsc r/w 8 00h ffbeh v sync separation circuit up/down counter register vsudc 8 ffbfh v sync separation circuit compare register vscmp 8 ffh ffc0h standby control register stbc 8 0011 000 ffc4h execution speed select register mm w 8 20h ffceh cpu clock status register pcs r 8 00h ffcfh oscillation stabilization time specification register osts w 8 ffe0h interrupt control register (intp0) pic0 r/w 8 43h ffe1h interrupt control register (intcpt3) cptic3 8 ffe2h interrupt control register (intcpt2) cptic2 8 ffe3h interrupt control register (intcr12) cric12 8 ffe4h interrupt control register (intcr00) cric00 8 ffe5h interrupt control register (intclr1) clric1 8 ffe6h interrupt control register (intcr10) cric10 8 remark cleared to 0: counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
29 m pd784927, 784928, 784927y, 784928y data sheet u12255ej2v0ds00 table 3-1. special function registers (5/5) address special function register (sfr) name symbol r/w bit bit units for manipulation after clearing length 1 bit 8 bits 16 bits reset ffe7h interrupt control register (intcr01) cric01 r/w 8 43h ffe8h interrupt control register (intcr02) cric02 8 ffe9h interrupt control register (intcr11) cric11 8 ffeah interrupt control register (intcpt1) cptic1 8 ffebh interrupt control register (intcr20) cric20 8 ffech interrupt control register (intiic) note 1 iicic 8 ffedh interrupt control register (inttb) tbic 8 ffeeh interrupt control register (intad) adic 8 ffefh interrupt control register (intp2) note 2 pic2 8 interrupt control register (intcr40) note 2 cric40 fff0h interrupt control register (intudc) udcic 8 fff1h interrupt control register (intcr30) cric30 8 fff2h interrupt control register (intcr50) cric50 8 fff3h interrupt control register (intcr13) cric13 8 fff4h interrupt control register (intcsi1) csiic1 8 fff5h interrupt control register (intw) wic 8 1000011 fff6h interrupt control register (intviss) visic 8 43h fff7h interrupt control register (intp1) pic1 8 fff8h interrupt control register (intp3) pic3 8 fffah interrupt control register (intcsi2) csiic2 8 notes 1. m pd784928y subseries only. 2. pic2 and cric40 are at the same address (register). remark cleared to 0: counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
m pd784927, 784928, 784927y, 784928y 30 data sheet u12255ej2v0ds00 3.4 ports the m pd784927 is provided with the ports shown in figure 3-3. table 3-2 shows the function of each port. figure 3-4. port configuration table 3-2. port function name pin name function specification of pull-up resistor port 0 p00-p07 can be set in input or output mode in pull-up resistors are connected to all 1-bit units. pins in input mode. port 2 p20-p23 input port pull-up resistors are connected to pins p22 and p23. port 3 p30-p37 can be set in input or output mode in pull-up resistors are connected to all pins 1-bit units. in input mode. port 4 p40-p47 can be set in input or output mode in 1-bit units. can directly drive led. port 5 p50-p57 can be set in input or output mode in port 6 p60-p67 1-bit units. port 7 p70-p77 input port pull-up resistor is not provided. port 8 p80, p82-p87 can be set in input or output mode in pull-up resistors are connected to all pins port 9 p90-p96 1-bit units. in input mode. port 10 p100-p103 input port pull-up resistor is not provided. port 11 p110-p113 p00 p07 port 0 p40 p47 port 4 p50 p57 port 5 port 6 p60 p67 port 8 p82 p87 port 9 p90 p96 p80 p70-p77 8 port 7 port 10 p100 p103 port 11 p110 p113 p20 p23 port 2 p30 p37 port 3
m pd784927, 784928, 784927y, 784928y 31 data sheet u12255ej2v0ds00 3.5 real-time output port a real-time output port consists of a port output latch and a buffer register (refer to figure 3-5 ). the function to transfer the data prepared in advance in the buffer register to the output latch when a trigger such as a timer interrupt occurs, and output the data to an external device is called a real-time output function. a port used in this way is called a real-time output port (rtp). table 3-3 shows the real-time output ports of the m pd784927. table 3-4 shows the trigger sources of rtps. figure 3-5. configuration of rtp table 3-3. bit configuration of rtp rtp shared with: number of bits of number of bits that can remark real-time output data be specified as rtp rtp0 port 0 4 bits 2 channels or 4-bit units 8 bits 1 channel rtp8 port 8 1 bit 1 channel and 1-bit units pseudo v sync output: 1 channel (rtp80) 2 bits 1 channel head amplifier switch: 1 channel (rtp82) chrominance rotation signal output: 1 channel (rtp83) table 3-4. trigger sources of rtp trigger source intcr00 intcr01 intcr02 intcr13 intcr50 intp0 remark rtp rtp0 high-order 4 bits low-order 4 bits all 8 bits rtp8 bit 0 note 1 bits 2 and 3 note 2 notes 1. select one of the four trigger sources. 2. when the real-time output port mode is set by the port mode control register 8 (pmc8), the hasw and rot-c signals that are set by the head amplifier switch output control register (hapc) are directly output. the hasw and rot-c signals are synchronized with hsw output (tm0-cr00 coincidence signal). however, the set signal is output immediately when the hapc register is rewritten. buffer register port output latch port output trigger
m pd784927, 784928, 784927y, 784928y 32 data sheet u12255ej2v0ds00 figures 3-6 and 3-7 show the block diagrams of rtp0 and rtp8. figure 3-8 shows the types of rtp output trigger sources. figure 3-6. block diagram of rtp0 remark intcr01: tm0-cr01 coincidence signal intcr02: tm0-cr02 coincidence signal figure 3-7. block diagram of rtp8 00 sel rotc sel hasw sel env pb mod2 pb mod1 pb mod0 head amplifier output control register (hapc) 8 00 port 8 buffer register l (p8l) 8 0 p8l4 sel md80 p8l2 0 p8l0 internal bus hasw, rot-c control circuit pseudo v sync output control circuit p83 p82 p80 8 h sync superimposition circuit output latch (p8) tm0-cr00 coincidence signal trg p80 pmc80 0 pmc82 pmc83 pmc8 8 4 4 44 8 intp0 intcr01 intcr02 p07 p00 p0h p0l real-time output port 0 control register (rtpc) output trigger control circuit internal bus buffer register output latch (p0)
m pd784927, 784928, 784927y, 784928y 33 data sheet u12255ej2v0ds00 figure 3-8. types of rtp output trigger sources tm0 cr00 cr01 cr02 tm1 cr10 cr11 cr12 cr13 tm5 cr50 real-time output port 0 control register (rtpc) selector selector intp0 interrupt and timer output interrupt and timer output interrupt interrupt capture trigger of p0h trigger of p0l trigger of p82 and p83 trigger of p80 trigger source select register 0 (trgs0)
m pd784927, 784928, 784927y, 784928y 34 data sheet u12255ej2v0ds00 rtp80 can output low-level, high-level, and high-impedance values real-time. because rtp80 can superimpose a horizontal sync signal, it can be used to create pseudo vertical sync signal. when rtp80 is set in the pseudo v sync output mode, it repeatedly outputs a specific pattern when an output trigger occurs. figure 3-9 shows the operation timing of rtp80. figure 3-9. example of operation timing of rtp80 (a) when h sync signal is superimposed (b) pseudo v sync output mode high level high impedance low level trigger signal p80 high level high impedance low level trigger signal p80
m pd784927, 784928, 784927y, 784928y 35 data sheet u12255ej2v0ds00 3.6 super timer unit the m pd784927 is provided with a super timer unit that consists of the timers, and vcr special circuits such as a viss detection circuit and a v sync separation circuit, etc., shown in table 3-5. table 3-5. configuration of super timer unit unit name timer/counter resolution maximum register remark count time timer 0 tm0 1 m s 65.5 ms cr00 controls delay of video head switching signal (16-bit timer) cr01 controls delay of audio head switching signal cr02 controls pseudo v sync output timing ec ecc0, ecc1, creates internal head switching signal (8-bit counter) ecc2, ecc3 free frc 125 ns 524 ms cpt0 detects reference phase (to control drum phase) running (22-bit counter) cpt1 detects phase of drum motor (to control drum counter phase) cpt2 detects speed of drum motor (to control drum speed) cpt3 detects speed of capstan motor (to control speed of capstan motor) cpt4, cpt5 detects remaining tape for reel fg timer 1 tm1 1 m s 65.5 ms cr10 playback: creates internal reference signal (16-bit timer) recording: buffer oscillator in case v sync is missing cr11 controls recctl output timing cr12 detects phase of capstan motor (to control capstan phase) cr13 controls v sync mask as noise preventive measures tm3 1 m s or 65.5 ms or cr30, cr31 controls duty detection timing of pbctl signal (16-bit timer) 1.1 m s 71.5 ms cpt30 measures cycle of pbctl signal edv edvc divides cfg signal frequency (8-bit counter) timer 2 tm2 1 m s 65.5 ms cr20 can be used as interval timer (to control system) (16-bit timer) timer 4 tm4 2 m s 131 ms cr40 detects duty of remote controller signal (to decode (16-bit timer) remote controller signal) cr41 measures cycle of remote controller signal (to de code remote controller signal) timer 5 tm5 2 m s 131 ms cr50 can be used as interval timer (to control system) (16-bit timer) up/down udc udcc creates linear tape counter counter (5-bit counter) pwm pwm0, pwm1, 16-bit resolution (carrier frequency: 62.5 khz) output unit pwm5 pwm2, pwm3, 8-bit resolution (carrier frequency: 62.5 khz) pwm4
m pd784927, 784928, 784927y, 784928y 36 data sheet u12255ej2v0ds00 (1) timer 0 unit timer 0 unit creates head switching signal and pseudo v sync output timing from the pg and fg signals of the drum motor. this unit consists of an event counter (ec: 8 bits), compare registers (ecc0 through ecc3), a timer (tm0: 16 bits), and compare registers (cr00 through cr02). a signal indicating coincidence between the value of timer 0 and the value of a compare register can be used as the output trigger of the real-time output port. (2) free running counter unit the free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed of the capstan motor. this unit consists of a free running counter (frc), capture registers (cpt0 through cpt5), a v sync separation circuit, and a h sync separation circuit. (3) timer 1 unit timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the recctl signal, detects the phase of the capstan motor, and detects the duty factor of the pbctl signal. this unit consists of the following three groups: timer 1 (tm1), compare registers (cr10, cr11, and cr13), and capture register (cr12) timer 3 (tm3), compare registers (cr30 and cr31), and capture register (cpt30) event divider counter (edv) and compare register (edvc) the tm1-cr13 coincidence signal can be used for automatic unmasking of v sync or as the output trigger of the real-time output port.
m pd784927, 784928, 784927y, 784928y 37 data sheet u12255ej2v0ds00 figure 3-10. block diagram of super timer unit (tm0, frc, tm1) divider selector ec ecc3 ecc2 ecc1 ecc0 f/f f/f writes 00h to ec clear selector mask selector selector tm0 cr00 cr01 cr02 clear intcr00 rtp pto00 intcr01 rtp, a/d pto01 intcr02 rtp, a/d pto02 (superimposition) (superimposition) to p80 selector h sync separation circuit v sync separation circuit selector mask selector selector selector selector selector tm3 cr30 cr31 cpt30 clear selector ctl f/f fflvl edv edvc clear capture selector frc cpt0 cpt1 cpt2 cpt3 cpt4 cpt5 tm1 cr10 cr11 cr12 clear cr13 capture capture capture capture capture capture capture intclr1 intcpt1 intcpt2 intcpt3 intp3 intcr10 intcr11 intcr12 intcr13 intcr30 pto10 pto11 to pbctl signal input block output control circuit selector selector output control circuit output control circuit dpgin dfgin csyncin reel0in reel1in cfgin pbctl pto10 pto11 analog circuit selector output control circuit output control circuit selector
m pd784927, 784928, 784927y, 784928y 38 data sheet u12255ej2v0ds00 (4) timer 2 unit timer 2 unit is a general-purpose 16-bit timer unit. this unit consists of a timer (tm2) and a compare register (cr20). the timer is cleared when the tm2-cr20 coincidence signal occurs, and at the same time, an interrupt request is generated. figure 3-11. block diagram of timer 2 unit (5) timer 4 unit timer 4 unit is a general-purpose 16-bit timer unit. this unit consists of a timer (tm4), a capture/compare register (cr40), and a capture register (cr41). the value of the timer is captured to cr40/cr41 when the intp2 signal is input. this timer can be used to decode a remote controller signal. figure 3-12. block diagram of timer 4 unit (6) timer 5 unit timer 5 unit is a general-purpose 16-bit timer unit. this unit consists of a timer (tm5) and a compare register (cr50). the timer is cleared by the tm5-cr50 coincidence signal, and at the same time, an interrupt request is generated. figure 3-13. block diagram of timer 5 unit tm2 cr20 clear intcr20 intcr40 mask clear tm4 cr40 cr41 selector intp2 clear intcr50 rtp, a/d tm5 cr50
m pd784927, 784928, 784927y, 784928y 39 data sheet u12255ej2v0ds00 (7) up/down counter unit the up/down counter unit is a counter that realizes a linear time counter. this unit consists of an up/down counter (udc) and a compare register (udcc). the up/down counter counts up the rising edges of pbctl and counts down the falling edges of pbctl. when the value of the up/down counter coincides with the value of the compare register, or when the counter underflows, an interrupt request is generated. figure 3-14. block diagram of up/down counter unit (8) pwm output unit the pwm output unit has three 16-bit accuracy output lines (pwm0, pwm1, and pwm5) and 8-bit accuracy output lines (pwm2 through pwm4). the carrier frequency of all the output lines is 62.5 khz (f clk = 8 mhz). pwm0 and pwm1 can be used to control the drum motor and capstan motor. figure 3-15. block diagram of 16-bit pwm output unit intudc udc udcc edvc output selector selector selector selector pto10 pto11 pbctl p77 selud up/down internal bus 16 8 8 8 15 8 7 0 pwmn (n = 0, 1, 5) reload to selector reload control reload 16 mhz 8-bit down counter 1/256 pwm pulse generation circuit 8-bit counter output control circuit reset pwmn pwmc0
m pd784927, 784928, 784927y, 784928y 40 data sheet u12255ej2v0ds00 figure 3-16. block diagram of 8-bit pwm output unit (9) viss detection circuit figure 3-17. block diagram of viss detection circuit pwm2 8-bit comparator pwm3 8-bit comparator pwm4 8-bit comparator pwmc1 pwm counter pwm4 pwm3 pwm2 16 mhz internal bus output control circuit output control circuit output control circuit selector vudc (8-bit up/down counter) vudst (vudc value setting register) viss malfunction prevention circuit vsft0 (shift register 0) vsft1 (shift register 1) vcmp (compare register) vps (viss pulse pattern setting register) cfg signal f clk /16 f clk /64 f clk /256 pbctl up/down coincidence intviss
m pd784927, 784928, 784927y, 784928y 41 data sheet u12255ej2v0ds00 (10) v sync separation circuit figure 3-18. block diagram of v sync separation circuit 3.7 serial interface the m pd784927 is provided with the serial interfaces shown in table 3-6. data can be automatically transmitted or received through these serial interfaces, when the macro service is used. table 3-6. types of serial interfaces name function serial interface channel 1 clocked serial interface (3-wire) bit length: 8 bits clock rate: external clock/31.25 khz/62.5 khz/125 khz/250 khz/500 khz/1 mhz (f clk = 8 mhz) msb first/lsb first selectable serial interface channel 2 clocked serial interface (3-wire) bit length: 8 bits clock rate: external clock/31.25 khz/62.5 khz/125 khz/250 khz/500 khz/1 mhz (f clk = 8 mhz) msb first/lsb first selectable busy/strb control function serial interface channel 3 i 2 c bus interface for multimaster c sync signal f clk /8 f clk /4 "00" s r q v sync f/f digital noise rejection circuit v sync selector vsudc (8-bit up/down counter) vscmp (8-bit compare register) selector
m pd784927, 784928, 784927y, 784928y 42 data sheet u12255ej2v0ds00 (1) serial interface channels 1, 2 figure 3-19. block diagram of serial interface channel n (n = 1 or 2) remark the circuits enclosed in the broken line are provided to serial interface channel 2 only. sion register csimn register intcsin selector f clk /8 f clk /16 f clk /32 f clk /64 f clk /128 f clk /256 csic2 register selector strb busy detection circuit strobe generation circuit serial clock counter sin /busy son sckn internal bus internal bus
m pd784927, 784928, 784927y, 784928y 43 data sheet u12255ej2v0ds00 (2) serial interface channel 3 ( m pd784928y subseries only) this channel transfers 8-bit data with multiple devices using two lines: serial clock (scl) and serial data bus (sda). it conforms to the i 2 c bus format, and can output a start condition, data, and stop condition onto the serial data bus during transmission. this data is automatically detected by hardware during reception. scl and sda are open-drain output pins and therefore, must be connected with a pull-up resistor. figure 3-20. serial interface channel 3 master cpu1 slave cpu1 sda scl master cpu2 slave cpu2 address 1 sda +v dd serial data bus serial clock scl slave cpu3 address 2 sda scl slave ic address 3 sda scl slave ic address n sda scl +v dd
m pd784927, 784928, 784927y, 784928y 44 data sheet u12255ej2v0ds00 3.8 a/d converter the m pd784927y has an analog-to-digital (a/d) converter with 12 multiplexed analog inputs (ani0 through ani11). this a/d converter is of successive approximation type, and the conversion result is held by an 8-bit a/d conversion result register (adcr) (conversion time: 10 m s at f clk = 8 mhz). a/d conversion can be started in the following two modes: hardware start : conversion is started by a hardware trigger note . software start : conversion is started by setting a bit of the a/d converter mode register (adm). after conversion has been started, the a/d converter operates in the following modes: scan mode : sequentially selects more than one analog input to obtain data to be converted from all the pins. select mode: use only one pin for analog input to obtain successive data to be converted. when the conversion result is transferred to adcr, interrupt request intad is generated. by processing this interrupt with the macro service, the conversion result can be successively transferred to memory. a mode in which starting a/d conversion of the next pin is kept pending until the value of adcr is read is also available. when this ode is used, reading the conversion result by mistake when timing is shifted because an interrupt is disabled can be prevented. note a hardware trigger is the following coincidence signals, one of which is selected by the trigger source select register 1 (trgs1): tm0-cr01 coincidence signal tm0-cr02 coincidence signal tm1-cr13 coincidence signal tm5-cr50 coincidence signal
m pd784927, 784928, 784927y, 784928y 45 data sheet u12255ej2v0ds00 figure 3-21. block diagram of a/d converter 3.9 vcr analog circuits the m pd784927 is provided with the following vcr analog circuits: ctl amplifier recctl driver (rewritable) dpg amplifier dfg amplifier dpfg separation circuit (ternary separation circuit) cfg amplifier reel fg comparator (2 channels) csync comparator ani0 ani1 ani2 ani3 ani11 . . . . . . input selector selector tm0-cr01 coincidence tm0-cr02 coincidence tm1-cr13 coincidence tm5-cr50 coincidence trigger source select register 1 (trgs1) successive approximation register (sar) a/d conversion result register (adcr) a/d converter mode register (adm) intad 16 8 8 conversion trigger trigger enable a/d conversion end interrupt internal bus av ref av ss2 r/2 r r/2 tap selector sample & hold circuit series resistor string voltage comparator delay detection circuit control circuit adm.7 (cs) 1 : on
m pd784927, 784928, 784927y, 784928y 46 data sheet u12255ej2v0ds00 (1) ctl amplifier/recctl driver the ctl amplifier is used to amplify the playback control (pbctl) signal that is reproduced from the ctl signal recorded on a vcr tape. the gain of the ctl amplifier is set by the gain control register (ctlm). thirty-two types of gains can be set in increments of about 1.78 db. the m pd784927 is also provided with a gain control signal generation circuit that monitors the status of the amplifier output to perform optimum gain control by software. the gain control signal generation circuit generates a ctl detection flag that identifies the amplitude status of the ctl amplifier output. by using this ctl detection flag, the gain of the ctl amplifier can be optimized. the recctl driver writes a control signal onto a vcr tape. this driver operates in two modes: rec mode that is used for recording, and rewrite mode used to rewrite the viss signal. the output status of the recctl pin is changed by hardware, by using the timer output from the super timer unit as a trigger. figure 3-22. block diagram of ctl amplifier and recctl driver + - + - tm1-cr13 coincidence signal tm1-cr11 coincidence signal tm3-cr30 coincidence signal tom1.4-tom1.6 selector recctl driver ampc. 1 ctl head ani11 ctldly recctl+ recctl - v ref ampc. 1 ctl detection flag s (ampm0. 3) ctl detection flag l (ampm0. 1) ctl detection flag clear (1 write to ampm0. 6) pbctl signal (to timer unit) ctlm. 0-ctlm. 4 ctlin ctlout1 ctlout2 gain control signal generation circuit waveform shaping circuit ctlmon ( to p67 )
m pd784927, 784928, 784927y, 784928y 47 data sheet u12255ej2v0ds00 (2) dpg amplifier, dfg amplifier, and dfpg separation circuit the dpg amplifier converts the drum pg (dpg) signal that indicates the phase information of the drum motor into a logic signal. the dfg amplifier amplifies the drum fg (dfg) signal that indicates the speed information of the drum motor. the dpfg separation circuit (ternary separation circuit) separates a drum pfg (dpfg) signal having speed and phase information into a dfg and dpg signals. figure 3-23. block diagram of dpg amplifier, dfg amplifier, and dpfg separation circuit + dfgin v ref v ref ampm0.0 dpfg separation circuit (ternary separation circuit) ampc.2 ampm0.2 1 0 1 ampm0.2 0 1 0 ampc.2 dfg signal (to timer unit) ampm0.2 drum fg signal or drum pfg signal ampc.2 ampc.7 v ref ampm0.0 dpgin drum pg signal v ref dpg comparator ampc.2 ampm0.2 ampc.2 1 0 1 0 + dpg amplifier 0 : on dpg signal (to timer unit) selector selector selector selector dfg amplifier dpgmon (to p65) dfgmon (to p64)
m pd784927, 784928, 784927y, 784928y 48 data sheet u12255ej2v0ds00 (3) cfg amplifier the cfg amplifier amplifies the capstan fg (cfg) signal that indicates the speed information of the capstan motor. this amplifier consists of an operational amplifier and a comparator. the gain of the operational amplifier is set by using an external resistor. when the gain of the operational amplifier is set to 50 db, the output duty accuracy of the cfg signal can be improved to 50.0 0.3%. figure 3-24. block diagram of cfg amplifier (4) reel fg comparators the reel fg comparator converts a reel fg signal that indicates the speed information of the reel motor into a logic signal. two comparators, one for take-up and the other for supply, are provided. figure 3-25. block diagram of reel fg comparators + - cfg signal (to timer unit) v ref v ref ampc.3 cfg amplifier cfgin cfgampo + - ampc.3 cfgcpin selector ampc.3 1 0 cfg comparator ampm0.0 capstan fg signal cfgmon (to p66) ampc.6 ampc.6 1 0 ampm0.0 reel0in v ref supply reel signal reel fg comparator reel fg0 signal (to timer unit) ampc.6 1 0 ampm0.0 reel1in v ref take-up reel signal reel fg comparator reel fg1 signal (to timer unit) selector selector
m pd784927, 784928, 784927y, 784928y 49 data sheet u12255ej2v0ds00 (5) csync comparator the csync comparator converts the compsync signal into a logic signal. figure 3-26. block diagram of compsync comparator (6) reference amplifier the reference amplifier generates a reference voltage (v ref ) to be supplied to the internal amplifiers and comparators of the m pd784927. figure 3-27. block diagram of reference amplifier remark multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators. ampc.5 ampc.5 1 0 ampm0.0 csyncin v ref comp sync signal csync comparator c sync signal (to timer unit) selector ampm1.7 - + vrefc av dd1 av ss1 encap (ampc.3) v ref (cfg amplifier) - + v ref (cfg amplifier) - + enctl (ampc.1) v ref (ctl amplifier) - + v ref endrum (ampc.2) enreel (ampc.6) encsyn (ampc.5) dfg amplifier, dpg comparator, reel fg comparator, and csync comparator)
m pd784927, 784928, 784927y, 784928y 50 data sheet u12255ej2v0ds00 (7) analog circuit monitor function this function is to output the following signals to port pins, and is mainly used for debugging. ? comparator output of ctl amplifier ? ctlmon (multiplexed port: p67) ? comparator output of cfg amplifier ? cfgmon (multiplexed port: p66) ? comparator output of dpg amplifier ? dpgmon (multiplexed port: p65) ? comparator output of dfg amplifier ? dfgmon (multiplexed port: p64) 3.10 watch function the m pd784927 has a watch function that counts the overflow signals of the watch timer by hardware. as the clock, the subsystem clock (32.768 khz) is used. because this watch function is independent of the cpu, it can be used even while the cpu is in the standby mode (stop mode) or is reset. in addition, this function can be used at a low voltage of v dd = 2.7 v (min.). therefore, by using only the watch function with the cpu set in the standby mode or reset, a watch operation can be performed at a low voltage and low current consumption. in addition, the watch function can also be used while the cpu is in the normal operation mode, because a dedicated counter is provided. the watch function can be used to count up to about 17 years of data. the hardware watch counters (hw0 and hw1) are shared with external input counters. these counters execute counting at the falling edge of input to the p65 pin, and can be used to count the h sync signals. figure 3-28. block diagram of watch counter pm65 pmc65 p65 selector hw0 hw1 selector watch timer selector selector p65 edge detection pin level read wm.2 (enables/disables operation) wm.2 wm.6 to nmi generation block intw wm.7 wm.5 wm.4 subclock wm.1 normal fast forward 0 1 wm.2 (enables/disables operation) f xt (32.768 khz) 013 0 1 015013 cms5 wm.2 buz signal
m pd784927, 784928, 784927y, 784928y 51 data sheet u12255ej2v0ds00 3.11 clock output function the m pd784927 can output a square wave (with a duty factor of 50%) to the p60/strb/clo pin as the operating clock for the peripheral devices or other microcomputers. to enable or disable the clock output, and to set the frequency of the clock, the clock output mode register (clom) is used. when setting the frequency, the division ratio can be set to f clk /n (where n = 1, 2, 4, 8, 16, 32, 64, or 128) (f clk = f osc /2: f osc is the oscillation frequency of the resonator). figure 3-29 shows the block diagram of the clock output circuit. the clock output (clo) pin is shared with p60 and strb. figure 3-29. block diagram of clock output circuit remark f clk : internal system clock caution do not use the clock output function in the stop mode. clear enclo (clom.4) to 0 in the stop mode. figure 3-30. application example of clock output function clom7 clom6 clom5 enclo 0 selfrq2 selfrq1 selfrq0 clom f clk f clk /4 f clk /8 f clk /16 f clk /32 f clk /64 f clk /128 f clk /2 p60 (output latch) 1 0 reset p60/strb/clo selector selector pd784927 m pd7503a m clo sck1 si1 so1 cl1 sck so si lcd 24 system clock
m pd784927, 784928, 784927y, 784928y 52 data sheet u12255ej2v0ds00 3.12 buzzer output function the buz signal can be superimposed on p61 or p64. the buzzer output frequency can be generated from the subsystem clock frequency or main system clock frequency. figure 3-31 shows the block diagram of the buz output circuit. the buz signal can be also used for trimming the subsystem clock. figure 3-31. block diagram of buz output circuit wm4 wm5 2.048 khz 4.096 khz 32.768 khz clom5 clom6 f clk /512 f clk /1024 f clk /4096 f clk /2048 clom7 0 1 cms4 wm7 p61 (output latch) buz output buz output p64 (output latch) 0 0 1 1 p61/buz p64/buz selector selector selector selector selector
m pd784927, 784928, 784927y, 784928y 53 data sheet u12255ej2v0ds00 4. internal/external control function 4.1 interrupt function the m pd784927 has as many as 32 interrupt sources, including internal and external sources. for 28 sources, a high-speed interrupt processing mode such as context switching or macro service can be specified by software. table 4-1 lists the interrupt sources.
m pd784927, 784928, 784927y, 784928y 54 data sheet u12255ej2v0ds00 table 4-1. interrupt sources interrupt interrupt request source macro context macro service vector request priority service switching control word table type name trigger address address reset reset reset pin input no no 0000h non- nmi nmi pin input edge 0002h maskable maskable 0 intp0 intp0 pin input edge pic0 yes yes fe06h 0006h 1 intcpt3 edvc output signal (cpt3 capture) cptic3 fe08h 0008h 2 intcpt2 dfgin pin input edge (cpt2 capture) cptic2 fe0ah 000ah 3 intcr12 pbctl input edge/edvc output signal cric12 fe0ch 000ch (cr12 capture) 4 intcr00 tm0-cr00 coincidence signal cric00 fe0eh 000eh 5 intclr1 csyncin pin input edge clric1 fe10h 0010h 6 intcr10 tm1-cr10 coincidence signal cric10 fe12h 0012h 7 intcr01 tm0-cr01 coincidence signal cric01 fe14h 0014h 8 intcr02 tm0-cr02 coincidence signal cric02 fe16h 0016h 9 intcr11 tm1-cr11 coincidence signal cric11 fe18h 0018h 10 intcpt1 pin input edge/ec output signal cptic1 fe1ah 001ah (cpt1 capture) 11 intcr20 tm2-cr20 coincidence signal cric20 fe1ch 001ch 12 intiic end of i 2 c bus transfer iicic note fe1eh 001eh 13 inttb time base from frc tbic fe20h 0020h 14 intad a/d converter conversion end adic fe22h 0022h 15 intp2 intp2 pin input edge pic2 fe24h 0024h intcr40 tm4-cr40 coincidence signal cric40 16 intudc udc-udcc coincidence/udc underflow udcic fe26h 0026h 17 intcr30 tm3-cr30 coincidence signal cric30 fe28h 0028h 18 intcr50 tm5-cr50 coincidence signal cric50 fe2ah 002ah 19 intcr13 tm1-cr13 coincidence signal cric13 fe2ch 002ch 20 intcsi1 end of serial transfer (channel 1) csiic1 fe2eh 002eh 21 intw overflow of watch timer wic fe30h 0030h 22 intviss viss detection signal visic fe32h 0032h 23 intp1 intp1 pin input edge pic1 fe34h 0034h 24 intp3 intp3 pin input edge pic3 fe36h 0036h 25 intcsi2 end of serial transfer (channel 2) csiic2 fe3ah 003ah operand illegal operand of mov stbc, #byte or no no 003ch error location instruction software execution of brk instruction 003eh execution of brkcs instruction yes note m pd784928y subseries only. remark evdc : event divider compare register ec : event counter frc : free running counter mscw : macro service control register interrupt control register name
m pd784927, 784928, 784927y, 784928y 55 data sheet u12255ej2v0ds00 figure 4-1. differences in operation depending on interrupt processing mode notes 1. when the register bank switching function is used and when initial values are set in advance to the registers 2. selecting a register bank and saving pc and psw by context switching 3. restoring register bank, pc, and psw by context switching 4. saves pc and psw to stack and loads vector address to pc macro service context switching note 1 vectored interrupt note 1 vectored interrupt main routine main routine main routine main routine interrupt request generated macro service processing main routine main routine main routine note 2 note 4 note 4 note 3 interrupt processing sel rbn interrupt processing saving general-purpose register initializing general-purpose register restoring pc and psw interrupt processing restoring general-purpose register restoring pc and psw main routine
m pd784927, 784928, 784927y, 784928y 56 data sheet u12255ej2v0ds00 4.1.1 vectored interrupt when an interrupt request is acknowledged, an interrupt processing program is executed according to the data stored in the vector table area (the first address of the interrupt processing program created by the user). in addition, four levels of priorities can be specified by software. 4.1.2 context switching when an interrupt request is generated or when the brkcs instruction is executed, a specific register bank is selected by hardware, and execution branches to a vector address set in advance in the register bank. at the same time, the current contents of the program counter (pc) and program status word (psw) are saved to the registers in the register bank. because the contents of pc and psw are not saved to the stack area, execution can be branched to an interrupt processing routine more quickly than the vectored interrupt. figure 4-2. context switching operation when interrupt request is generated pc19-16 pc15-0 <7> 0h <2> save <6> exchange <5> save bits 8-11 of temporary register temporary register <1> save psw register bank n (n = 0-7) a b r5 r7 d h x c r4 r6 e l vp up v u t w register bank (0-7) <3> <4> switching register bank (rbs0-rbs2 ? n) rss ie ? 0 ? 0
m pd784927, 784928, 784927y, 784928y 57 data sheet u12255ej2v0ds00 4.1.3 macro service the macro service is a function to transfer data between the memory and a special function register (sfr) without intervention by the cpu. a macro service controller accesses the memory and sfr and directly transfers the data. because the status of the cpu is not saved or restored, data can be transferred more quickly than context switching. the processing that can be executed with the macro service is described below. figure 4-3. macro service (1) counter mode in this mode, the value of the macro service counter (msc) is decremented when an interrupt request occurs. this mode can be used to execute the division operation of an interrupt request or count the number of times an interrupt request has occurred. when the value of the macro service counter has been decremented to 0, a vectored interrupt occurs. (2) compound data transfer mode when an interrupt request occurs, data are simultaneously transferred from an 8-bit sfr to memory, a 16- bit sfr to memory (word), memory (byte) to an 8-bit sfr, and memory (word) to a 16-bit sfr (3 points max. for each transfer). this mode can also be used to exchange data, instead of transferring data. this mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/ timing by the serial output port. when the value of the macro service counter reaches to 0, a vectored interrupt request occurs. cpu memory sfr read write write read internal bus macro service controller msc - 1 sfr<4>-1 sfr<4>-2 sfr<4>-3 sfr<3>-1 sfr<3>-2 sfr<3>-3 sfr<2>-1 sfr<2>-2 sfr<2>-3 sfr<1>-1 sfr<1>-2 sfr<1>-3 . . . memory internal bus internal bus
m pd784927, 784928, 784927y, 784928y 58 data sheet u12255ej2v0ds00 (3) macro service type a when an interrupt request occurs, data is transferred from an 8-/16-bit sfr to memory (byte/word) or from memory (byte/word) to an 8-/16-bit sfr. data is transferred the number of times set in advance by the macro service counter. this mode can be used to store the result of a/d conversion or for automatic transfer (or reception) by the serial interface. because transfer data is stored at an address fe00h to feffh, if only a small quantity of data is to be transferred, the data can be transferred at high speeds. when the value of the macro service counter is decremented to 0, a vectored interrupt request occurs. (4) data pattern identification mode (viss detection mode) this mode of macro service is for detection of the viss signal and is used in combination with a pulse width detection circuit. when an interrupt request occurs, the content of bit 7 of an sfr (usually, tmc3) specified by sfr pointer 1 is shifted into the buffer area. at the same time, the data in the buffer area is compared with the data in the compare area. if the two data coincide, a vectored interrupt request is generated. when the value of the macro service counter is decremented to 0, a vectored interrupt request occurs. it can be specified by option that the value of an sfr (usually, cpt30) specified by sfr pointer 2 be multiplied by a coefficient and the result of this multiplication be stored to an sfr (usually, cr30) specified by sfr pointer 3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates). data storage buffer (memory) data n data n - 1 data 2 data 1 sfr internal bus data storage buffer (memory) data n data n - 1 data 2 data 1 sfr internal bus coefficient (memory) cpt30 tm3 cr30 multiplier buffer area (memory) compare area (memory) coincidence ctl f/f ( bit 7 of tmc3 ) vectored interrupt
m pd784927, 784928, 784927y, 784928y 59 data sheet u12255ej2v0ds00 4.1.4 application example of macro service (1) automatic transfer/reception of serial interface automatic transfer/reception of 3-byte data by serial interface channel 1 setting of macro service register: compound data transfer mode (exchange mode) si1 so1 macro service channel macro service control word 70 fe50h fe2eh macro service counter (msc = 2) memory pointer h (= fd) memory pointer l (= 50) ddccbbaa (= 01000100b) sfr pointer <2> (sfrp2 = 85h) sfr pointer <4> (sfrp4 = 85h) channel pointer (= 50h) mode register (= 10110011b) high-order address low-order address (exchange 2) (before transfer) sio1 (ff85h) <3> <2> transmit data 2 transmit data 3 (transmit data 1) fd52h fd51h fd50h (after transfer) receive data 1 receive data 2 fd51h fd50h ( receive data 3 is the data of sio1. ) (exchange 1) transfer is started by writing transmit data 1 to sio1 by software. <1>
m pd784927, 784928, 784927y, 784928y 60 data sheet u12255ej2v0ds00 (2) reception operation of serial interface transfer of receive data by serial interface channel 1 (16 bytes) setting of macro service mode register: macro service type a (1-byte data transfer from sfr to memory) fe7fh fe2eh sio1 (ff85h) si1 internal ram msc 0fh sfr pointer 85h channel pointer (= 7fh) mode register (= 00010001b) starts macro service when intcsi1 occurs setting of number of transfers low-order 8 bits of address of sio1 register
m pd784927, 784928, 784927y, 784928y 61 data sheet u12255ej2v0ds00 (3) viss detection operation setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte compari- son) macro service counter (msc = ffh) sfr pointer 2 (sfrp2 = 56h) coefficient (6eh: 43%) sfr pointer 3 (sfrp3 = 5ch) sfr pointer 1 (sfrp1 = 3bh) buffer size specification register (64 bits: 8h) 11111111 11111110 compare area pointer (high): 10h compare area pointer (low): 50h channel pointer (= 50h) mode register (= 00010100b) cpt30 tm3 cr30 tmc3 00000000 00000000 0 high-order address fe50h fe0ch 8 bytes multiplier bit 7 1050h 8 bytes coincidence (vectored interrupt) (ctl signal input edge detection interrupt) low-order address
m pd784927, 784928, 784927y, 784928y 62 data sheet u12255ej2v0ds00 4.2 standby function the standby function is to reduce the power consumption of the chip and is used in the following modes: mode function halt mode stops operating clock of cpu. reduces average power consumption when used in combination with normal mode for intermittent operation stop mode stops oscillator. stops all internal operations of chip to minimize power consump- tion to leakage current only low power consumption mode stops main system clock with subsystem clock used as system clock. cpu can operate with subsystem clock to reduce current consumption low power consumption halt mode standby function in low power consumption mode. stops operating clock of cpu. reduces power consumption of overall system these modes are programmable. the macro service can be started in the halt mode. figure 4-4. status transition of standby function notes 1. nmi input means starting nmi by nmi pin input, watch interrupt, or key interrupt input. 2. unmasked interrupt request low power consumption mode (subsystem clock operation) normal operation waits for stabilization of oscillation low power consumption halt mode (standby) stop mode (standby) halt mode (standby) macro service nmi input note 1 intw, intp2 interrupt request sets low power consumption halt mode sets low power consumption mode restores normal operation end of oscillation stabilization period nmi input note 1 reset input sets stop unmasked interrupt request sets halt interrupt request note 2 reset input macro service request end of one processing end of macro service macro service request end of one processing
m pd784927, 784928, 784927y, 784928y 63 data sheet u12255ej2v0ds00 figure 4-5. relations among nmi, watch interrupt, and key interrupt when stop mode is released selector intm0.0 nmi intp1 intp2 key0 key1 key2 key3 key4 mask mask mask keyc.6 keyc.5 keyc.4 clear standby control block interrupt control block selector wm.6 wm.3 s r q keyc.7 cleared when "0" is written to keyc.7 s r q keyc.0 cleared when "0" is written to keyc.0 watch timer intw (ovf) divides intw by 128 (hw0l.7) mask latch
m pd784927, 784928, 784927y, 784928y 64 data sheet u12255ej2v0ds00 4.3 clock generation circuit the clock generation circuit generates and controls the internal system clock (clk) to be supplied to the cpu and peripheral circuits. figure 4-6 shows the configuration of this circuit. figure 4-6. block diagram of clock generation circuit notes 1. f xx : oscillation frequency, ( ): in low-frequency oscillation mode. 2. the peripheral hardware units that can operate with the subsystem clock have some restrictions. for details, refer to m pd784928, 784928y subseries users manual-hardware (u12648e) . x1 x2 16 mhz or 8 mhz xt1 xt2 32.768 khz pd784927 m main system clock oscillation circuit oscillation stop from standby control block subsystem clock oscillation circuit f xt stbc.7 oscillation stop 1/2 watch timer hardware watch function watch interrupt normal mode low-frequency oscillation mode cc.7 selector 1/2 1/2 1/2 oscillation stabilization timer stbc.4, 5 stbc.6 f xx /16 (f xx /8) note 1 selector selector f xx /8 (f xx /4) note 1 f xx /4 (f xx /2) note 1 f xx /2 (f xx ) note 1 cpu peripheral hardware operation clock note 2 f clk f xx
m pd784927, 784928, 784927y, 784928y 65 data sheet u12255ej2v0ds00 4.4 reset function when a low-level signal is input to the reset pin, the system is reset, and each hardware unit is initialized (reset status). during the reset period, oscillation of the system clock is unconditionally stopped, so that the current consumption of the overall system can be reduced. when the reset pin goes high, the reset status is cleared. after the count time of the oscillation stabilization timer (32.8 ms at 16 mhz or 65.6 ms at 8 mhz) has elapsed, the contents of the reset vector table are set to the program counter (pc), and execution branches to the address set to the pc, and the program is executed starting from the branch destination address. therefore, execution can be reset and started from any address. figure 4-7. oscillation of main system clock during reset period the reset pin is provided with an analog delay noise rejection circuit to prevent malfunctioning due to noise. figure 4-8. accepting reset signal main system clock oscillation circuit f clt reset input oscillation stabilization timer count time during reset, oscillation is unconditionally stopped. reset input internal reset signal internal clock analog delay analog delay analog delay oscillation stabilization time
m pd784927, 784928, 784927y, 784928y 66 data sheet u12255ej2v0ds00 5. instruction set (1) 8-bit instructions (( ): combination realized by using a as r) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla 2nd operand # byte a r saddr sfr !addr16 mem r3 [whl+] [whlC] n none note 2 r' saddr' !!addr24 [saddrp] pswl 1st operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (xch) (add) note 1 (add) note 1 (add) notes 1,6 (add) note 1 add note 1 add note 1 (add) note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 (add) note 1 movm note 4 [tdeC] (mov) movbk note 5 (add) note 1 movm note 4 notes 1. addc, sub, subc, and, or, xor, and cmp are the same as add. 2. either the second operand is not used, or the second operation is not an operand address. 3. rol, rorc, rolc, shr, and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as movbk. 6. if saddr2 instead of saddr is used in this combination, the code length of some instructions is short.
m pd784927, 784928, 784927y, 784928y 67 data sheet u12255ej2v0ds00 2nd operand # word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 rp' saddrp !!addr24 [saddrp] 1st operand [%saddrg] ax (movm) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) ( xchw ) note 3 (xchw) xchw xchw (xchw) (addw) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw (2) 16-bit instructions (( ): combination realized by using ax as rp) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw notes 1. subw and cmpw are the same as addw. 2. either the second operand is not used, or the second operation is not an operand address. 3. if saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 4. muluw and divux are the same as mulw.
m pd784927, 784928, 784927y, 784928y 68 data sheet u12255ej2v0ds00 (3) 24-bit instructions (( ): combination realized by using whl as rg) movg, addg, subg, incg, decg, push, pop 2nd operand # imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note rg' 1st operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note either the second operand is not used, or the second operation is not an operand address. (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset 2nd operand cy saddr.bit /saddr.bit none note sfr.bit /sfr.bit a.bit /a.bit x.bit /x.bit pswl.bit /pswl.bit pswh.bit /pswh.bit mem2.bit /mem2.bit iaddr16.bit /!addr16.bit 1st operand !addr24.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note either the second operand is not used, or the second operation is not an operand address.
m pd784927, 784928, 784927y, 784928y 69 data sheet u12255ej2v0ds00 (5) call/return and branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz operand of $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none instruction address basic bc note call call call call call call call callf callt brkcs brk instruction br br br br br br br br ret retcs reti retcsb retb compound bf instruction bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs
m pd784927, 784928, 784927y, 784928y 70 data sheet u12255ej2v0ds00 6. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd | v dd C av dd1 | 0.5 v C0.5 to +7.0 v av dd1 | v dd C av dd2 | 0.5 v C0.5 to +7.0 v av dd2 | av dd1 C av dd2 | 0.5 v C0.5 to +7.0 v av ss1 C0.5 to +0.5 v av ss2 C0.5 to +0.5 v input voltage vi C0.5 to v dd + 0.5 v analog input voltage v ian v dd 3 av dd2 C0.5 to av dd2 + 0.5 v (ani0-ani11) v dd < av dd2 C0.5 to v dd + 0.5 v output voltage v o C0.5 to v dd + 0.5 v low-level output current i ol pin 1 15 ma total of all pins 100 ma high-level output current i oh pin 1 C10 ma total of all pins C50 ma operating ambient temperature t a C10 to +70 c storage temperature t stg C65 to +150 c caution if the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. never exceed these values when using the product. operating conditions clock frequency operating ambient temperature (t a ) operating conditions supply voltage (v dd ) 4 mhz f xx 16 mhz C10 to +70 c all functions +4.5 to +5.5 v cpu function only +4.0 to +5.5 v 32 khz f xt 35 khz subclock operation +2.7 to +5.5 v (cpu, watch, and port functions only)
m pd784927, 784928, 784927y, 784928y 71 data sheet u12255ej2v0ds00 oscillator characteristics (main clock) (t a = C10 to +70 c, v dd = av dd = 4.0 to 5.5 v, v ss = av ss = 0 v) resonator recommended circuit parameter min. max. unit crystal resonator oscillation frequency (f xx ) 4 16 mhz oscillator characteristics (subclock) (t a = C10 to +70 c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) resonator recommended circuit parameter min. max. unit crystal resonator oscillation frequency (f xt ) 32 35 khz caution when using the main system clock and subsystem clock oscillator, wire the portion enclosed by the broken line in the above figures as follows to avoid the adverse influence of wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring in the neighborhood of a signal line through which a high alternating current flows. always keep the ground point of the capacitor of the oscillator to the same potential as v ss . do not ground the capacitor to a ground pattern to which a high current flows. do not extract signals from the oscillation circuit. exercise particular care in using the subsystem clock oscillator because the amplification factor of this circuit is kept low to reduce the current consumption. remark for the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x1 x2 v ss c1 c2 xt1 xt2 v ss c1 c2
m pd784927, 784928, 784927y, 784928y 72 data sheet u12255ej2v0ds00 dc characteristics (t a = C10 to +70 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit low-level input voltage v il1 pins other than those listed in note 1 below 0 0.3 v dd v v il2 pins listed in note 1 below 0 0.2 v dd v v il3 x1, x2 0 0.4 v high-level input voltage v ih1 pins other than those listed in note 1 below 0.7 v dd v dd v v ih2 pins listed in note 1 below 0.8 v dd v dd v v ih3 x1, x2 v dd C 0.5 v dd v low-level output voltage v ol1 i ol = 8.0 ma (pins in note 2 ) 1.0 v v ol2 i ol = 5.0 ma (pins in note 4 ) 0.6 v v ol3 i ol = 2.0 ma 0.45 v v ol4 i ol = 100 m a 0.25 v high-level output voltage v oh1 i oh = C1.0 ma v dd C 1.0 v v oh2 i oh = C100 m av dd C 0.4 v input leakage current i li 0 v i v dd 10 m a output leakage current i lo 0 v o v dd 10 m a v dd supply current i dd1 operation f xx = 16 mhz 30 50 ma mode f xx = 8 mhz (low-frequency os- cillation mode) internally, 8 mhz main clock operation f xt = 32.768 khz 50 80 m a subclock operation (cpu, watch, port) v dd = 2.7 v i dd2 halt mode f xx = 16 mhz 10 25 ma f xx = 8 mhz (low-frequency oscillation mode) internally, 8 mhz main clock operation f xt = 32.768 mhz 25 50 m a subclock operation (cpu, watch, port) v dd = 2.7 v data hold voltage v dddr stop mode 2.5 v data hold current note 3 i dddr stop mode subclock oscillates 18 50 m a v dddr = 5.0 v stop mode subclock oscillates 2.5 10 m a v dddr = 2.7 v stop mode subclock stops 0.2 7.0 m a v dddr = 2.5 v pull-up resistor r l v i = 0 v 25 55 110 k w notes 1. reset, ic, nmi, intp0-intp2, p61/sck1/buz, p63/si1, sck2, si2/busy, p65/hwin, p91/key0 to p95/key4 2. p40 to p47 3. in the stop mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and connect the xt1 pin to v dd . 4. p46, p47
m pd784927, 784928, 784927y, 784928y 73 data sheet u12255ej2v0ds00 ac characteristics cpu and peripheral circuit operation clock (t a = C10 to +70 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions typ. unit cpu operation clock cycle time t clk f xx = 16 mhz v dd = av dd = 4.0 to 5.5 v 125 ns cpu function only f xx = 16 mhz f xx = 8 mhz low-frequency oscillation mode (bit 7 of cc = 1) peripheral operation clock cycle time t clk1 f xx = 16 mhz 125 ns f xx = 8mhz low-frequency oscillation mode (bit 7 of cc = 1) serial interface (1) sion: n = 1 or 2 (t a = C10 to +70 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk input external clock 1.0 m s output f clk1 /8 1.0 m s f clk1 /16 2.0 m s f clk1 /32 4.0 m s f clk1 /64 8.0 m s f clk1 /128 16 m s f clk1 /256 32 m s serial clock high- and low-level widths t wskh input external clock 420 ns t wskl output internal clock t cysk /2 C 50 ns sin setup time (vs. sckn - )t sssk 100 ns sin hold time (vs. sckn - )t hssk 400 ns son output delay time (vs. sckn )t dssk 0 300 ns remarks 1. f clk1 : operating clock of peripheral circuit (8 mhz) 2. n = 1 or 2 (2) sio2 only (t a = C10 to +70 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. max. unit sck2(8) -? strb - t dstrb t wskh t cysk strobe high-level width t wstrb t cysk C 30 t cysk + 30 ns busy setup time t sbusy 100 ns (vs. busy detection timing) busy hold time t hbusy 100 ns (vs. busy detection timing) busy inactive ? sck2(1) t lbusy t cysk + t wskh remarks 1. the value in ( ) following sck2 indicates the number of sck2. 2. busy is detected after the time of (n + 2) x t cysk (n = 0, 1, and so on) in respect to sck2 (8) - . 3. busy inactive ? sck2 (1) is the value when data has been completely written to sio2.
m pd784927, 784928, 784927y, 784928y 74 data sheet u12255ej2v0ds00 i 2 c bus mode ( m pd784928y subseries only) parameter symbol standard mode high-speed mode unit min. max min max. scl clock frequency f clk 0 100 0 400 khz bus free time (between stop and start t buf 4.7 C 1.3 C m s conditions) hold time note 1 t hd : sta 4.0 C 0.6 C m s scl clock low-level width t low 4.7 C 1.3 C m s scl clock high-level width t high 4.0 C 0.6 C m s start/restart condition setup time t su : sta 4.7 C 0.6 C m s data hold cbus compatible master t hd : dat 5.0 C C C m s time i 2 c bus 0 note 2 C0 note 2 0.9 note 2 m s data setup time t su : dat 250 C 100 note 4 Cns sda and scl signal rise time t r C 1000 20+0.1cb note 5 300 ns sda and scl signal fall time t f C 300 20+0.1cb note 5 300 ns stop condition setup time t su : sto 4.0 C 0.6 C m s pulse width of spike restrained by input t sp CC050ns filter each bus line capacitative load cb C 400 C 400 pf notes 1. the first clock pulse is generated at the start condition after this period. 2. the device needs to internally supply a hold time of at least 300 ns for the sda signal to fill the undefined area at the falling edge of the scl (v ihmin . of the scl signal). 3. unless the device extends the low hold time (t low ) of the scl signal, it is necessary to fill only the maximum data hold time (t hd : dat ). 4. the high-speed mode i 2 c bus can be used in the standard mode i 2 c bus system. in this case, satisfy the following conditions: ? when the device does not extend the low hold time of the scl signal t su : dat 3 250 ns ? when the device extends the low hold time of the scl signal send the next data bit to the sda line before releasing the scl line (t rmax . + t su : dat = 1000 + 250 = 1250 ns : in the standard mode i 2 c bus specification) 5. cb: total capacitance of one bus line (unit: pf)
m pd784927, 784928, 784927y, 784928y 75 data sheet u12255ej2v0ds00 other operations (t a = C10 to +70 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol condition min. max. unit timer input signal low-level width t wctl when dfgin, cfgin, dpgin, reel0in, t clk1 ns or reel1in logic level is input timer input signal high-level width t wcth when dfgin, cfgin, dpgin, reel0in, t clk1 ns or reel1in logic level is input timer input signal valid edge input cycle t perin when dfgin, cfgin, or dpgin is input 2 m s csyncin low-level width t wcr1l when digital noise rejection circuit is not used 8t clk1 ns when digital noise rejection circuit is used 108t clk1 ns (bit 4 of intm2 = 0) when digital noise rejection circuit is used 180t clk1 ns (bit 4 of intm2 = 1) csyncin high-level width t wcr1h when digital noise rejection circuit is not used 8t clk1 ns when digital noise rejection circuit is used 108t clk1 ns (bit 4 of intm2 = 0) when digital noise rejection circuit is used 180t clk1 ns (bit 4 of intm2 = 1) digital noise rejected pulse width t wsep bit 4 of intm2 = 0 104t clk1 ns rejection circuit bit 4 of intm2 = 1 176t clk1 ns passed pulse width bit 4 of intm2 = 0 108t clk1 ns bit 4 of intm2 = 1 180t clk1 ns nmi low-level width t wnil v dd = av dd = 2.7 to 5.5 v 10 m s nmi high-level width t wnih v dd = av dd = 2.7 to 5.5 v 10 m s intp0, intp3 low-level widths t wipl0 2t clk1 ns intp0, intp3 high-level widths t wiph0 2t clk1 ns intp1, key0-key4 low-level widths t wipl1 mode other than stop mode 2t clk1 ns in stop mode, for releasing stop mode 10 m s intp1, key0-key4 high-level widths t wiph1 mode other than stop mode 2t clk1 ns in stop mode, for releasing stop mode 10 m s intp2 low-level width t wipl2 in normal mode, sampling = f clk 2t clk1 ns with main clock sampling = f clk /128 32 note m s normal mode, sampling = f clk 61 m s with subclock sampling = f clk /128 7.9 note ms in stop mode, for releasing stop mode 10 m s intp2 high-level width t wiph2 in normal mode, sampling = f clk 2t clk1 ns with main clock sampling = f clk /128 32 note m s normal mode, sampling = f clk 61 m s with subclock sampling = f clk /128 7.9 note ms in stop mode, for releasing stop mode 10 m s reset low-level width t wrsl 10 m s note if a high or low level is successively input two times during the sampling period, a high or low level is detected. remark t ckl1 : operating clock cycle time of peripheral circuit (125 ns)
m pd784927, 784928, 784927y, 784928y 76 data sheet u12255ej2v0ds00 clock output operation (t a = C10 to +70 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol condition min. max. unit clo cycle time t cycl nt 125 16000 ns clo low-level width t cll t cycl /2 25 37.5 8025 ns clo high-level width t clh t cycl /2 25 37.5 8025 ns clo rise time t clr 25 ns clo fall time t clf 25 ns remarks 1. n: system clock division 2. t = 1/f clk data hold characteristics (t a = C10 to +70 c, v dd = av dd = 2.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit low-level input voltage v il special pins (pins in note ) 0 0.1 v dddr v high-level input voltage v ih 0.9 v dddr v dddr v note reset, ic, nmi, intp0-intp2, p61/sck1/buz, p63/si1, sck2, si2/busy, p65/hwin, p91/key0-p95/ key4 watch function (t a = C10 to +70 c, v dd = av dd = 2.7 to 5.5 v, v ss = av ss = 0 v) parameter symbol condition min. max. unit subclock oscillation hold voltage v ddxt 2.7 v hardware watch function operating voltage v ddw 2.7 v subclock oscillation stop detection flag (t a = C10 to +70 c, v dd = av dd = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol condition min. max. unit oscillation stop detection width t oscf 45 m s a/d converter characteristics (t a = C10 to +70 c, v dd = av dd = av ref = 4.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit resolution 8 bit total error av ref = v dd 2.0 % quantization error 1/2 lsb conversion time t conv bit 4 of adm = 0 160t clk1 m s bit 4 of adm = 1 80t clk1 m s sampling time t samp bit 4 of adm = 0 32t clk1 m s bit 4 of adm = 1 16t clk1 m s analog input voltage v ian 0av ref v analog input impedance z an 1000 m w av ref current ai ref 0.4 1.2 ma
m pd784927, 784928, 784927y, 784928y 77 data sheet u12255ej2v0ds00 vref amplifier (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit reference voltage v ref 2.35 2.50 2.65 v charge current i chg sets ampm0.0 to 1 300 m a (pins in note ) note recctl+, recctlC, cfgin, cfgcpin, dfgin, dpgin, csyncin, reel0in, reel1in ctl amplifier (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit ctl+, C input resistance r ictl 2510k w feedback resistance r fctl 20 50 100 k w bias resistance r bctl 20 50 100 k w minimum voltage gain g ctlmin 17 20 22 db maximum voltage gain g ctlmax 71 75 db gain selecting step s gain 1.77 db same phase signal elimination ratio cmr dc, voltage gain: 20 db 50 db high comparator set voltage of waveform shaping v pbctlhs v ref + 0.47 v ref + 0.50 v ref + 0.53 v high comparator reset voltage of waveform shaping v pbctlhr v ref + 0.27 v ref + 0.30 v ref + 0.33 v low comparator set voltage of waveform shaping v pbctlls v ref C 0.53 v ref C 0.50 v ref C 0.47 v low comparator reset voltage of waveform shaping v pbctllr v ref C 0.33 v ref C 0.30 v ref C 0.27 v comparator schmitt width of waveform shaping v pbsh 150 200 250 mv high comparator voltage of ctl flag s v fsh v ref + 1.00 v ref + 1.05 v ref + 1.10 v low comparator voltage of clt flag s v fsl v ref C 1.10 v ref C 1.05 v ref C 1.00 v high comparator voltage of ctl flag l v flh v ref + 1.40 v ref + 1.45 v ref + 1.50 v low comparator voltage of ctl flag l v fll v ref C 1.50 v ref C 1.45 v ref C 1.40 v
m pd784927, 784928, 784927y, 784928y 78 data sheet u12255ej2v0ds00 cfg amplifier (ac coupling) (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit voltage gain 1 g cfg1 f i = 2 khz, open loop 50 db voltage gain 2 g cfg2 f i = 30 khz, open loop 34 db cfgampo high-level output current i ohcfg dc C1 ma cfgampo low-level output current i olcfg dc 0.1 ma high comparator voltage v cfgh v ref + 0.09 v ref + 0.12 v ref + 0.15 v low comparator voltage v cfgl v ref C 0.15 v ref C 0.12 v ref C 0.09 v duty accuracy p duty note 49.7 50.0 50.3 % note the conditions include the following circuit and input signal. input signal : sine wave input (5 mv p-p ) f i = 1 khz voltage gain: 50 db dfg amplifier (ac coupling) (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit voltage gain g dfg f i = 900 hz, open loop 50 db feedback resistance r fdfg 160 400 640 k w input protection resistance r idfg 150 w high comparator voltage v dfgh v ref + 0.07 v ref + 0.10 v ref + 0.14 v low comparator voltage v dfgl v ref C 0.14 v ref C 0.10 v ref C 0.07 v caution set the input resistance connected to the dfgin pin to 16 k w or below. connecting a resistor exceeding that value may cause the dfg amp to oscillate. ? 1 k w 330 k w 22 f cfgin cfgampo cfgcpin pd784927 0.01 f m m m
m pd784927, 784928, 784927y, 784928y 79 data sheet u12255ej2v0ds00 dpg amplifier (ac coupling) (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit voltage gain g dpg f i = 30 hz 20 db high comparator voltage v dpgh1 seldpghl0 = 0, seldpghl1 = 0 v ref + 0.02 v ref + 0.05 v ref + 0.08 v v dpgh2 seldpghl0 = 1, seldpghl1 = 0 v ref + 0.56 v ref + 0.60 v ref + 0.64 v v dpgh3 seldpghl0 = 0, seldpghl1 = 1 v ref C 0.44 v ref C 0.40 v ref C 0.36 v low comparator voltage v dpgl1 seldpghl0 = 0, seldpghl1 = 0 v ref C 0.08 v ref C 0.05 v ref C 0.02 v v dpgl2 seldpghl0 = 1, seldpghl1 = 0 v ref + 0.36 v ref + 0.40 v ref + 0.44 v v dpgl3 seldpghl0 = 0, seldpghl1 = 1 v ref C 0.64 v ref C 0.60 v ref C 0.56 v caution when both the seldpghl0 and seldpghl1 are set to 0, the dpg amplifier is not used. therefore, be sure to set ampc.7 (endpg) to 0. ternary separation circuit (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit input impedance z ipfg 20 50 100 k w high comparator voltage v pfgh v ref + 0.5 v ref + 0.7 v ref + 0.9 v low comparator voltage v pfgl v ref C 1.4 v ref C 1.2 v ref C 1.0 v csync comparator (ac coupling) (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit input impedance z icsyn 20 50 100 k w high comparator voltage v csynh v ref + 0.07 v ref + 0.10 v ref + 0.13 v low comparator voltage v csynl v ref C 0.13 v ref C 0.10 v ref C 0.07 v reel fg comparator (ac coupling) (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit input impedance z irlfg 20 50 100 k w high comparator voltage v rlfgh v ref + 0.02 v ref + 0.05 v ref + 0.08 v low comparator voltage v rlfgl v ref C 0.08 v ref C 0.05 v ref C 0.02 v recctl driver (t a = 25 c, v dd = av dd = 5 v, v ss = av ss = 0 v) parameter symbol condition min. typ. max. unit recctl+, C high-level output voltage v chrec i oh = C4 ma v dd C 0.8 v recctl+, C low-level output voltage v olrec i ol = 4 ma 0.8 v ctldly internal resistance r ctl 40 70 140 k w ctldly charge current i ohctl use of internal resistor C3 ma ctldly discharge current i olctl C3 ma
m pd784927, 784928, 784927y, 784928y 80 data sheet u12255ej2v0ds00 timing waveform ac timing test point serial transfer timing (sion: n = 1 or 2) t wskl t wskh t cysk t dssk t sssk t hssk input data output data sckn sin son 0.8 v dd or 2.2 v 0.8 v 0.8 v dd or 2.2 v 0.8 v test point
m pd784927, 784928, 784927y, 784928y 81 data sheet u12255ej2v0ds00 serial transfer timing (sio2 only) no busy processing continuation of busy processing end of busy processing caution when an external clock is selected as the serial clock, do not use the busy control or strobe control. t wskl t wskh t cysk 7 89101 2 t dstrb t wstrb active high busy invalid sck2 busy strb t wskl t wskh t cysk 78910 10+n t dstrb t wstrb active high sck2 busy strb t sbusy t sbusy t wskl t wskh t cysk 7 8 9 10+n 11+n active high sck2 busy t hbusy t lbusy 1
m pd784927, 784928, 784927y, 784928y 82 data sheet u12255ej2v0ds00 i 2 c bus mode ( m pd784928y subseries only) t low t r t hd : dat t f t high t hd : sta t su : sta t hd : sta t sp t su : sto t buf scl sda t su : dat stop condition start condition restart condition stop condition
m pd784927, 784928, 784927y, 784928y 83 data sheet u12255ej2v0ds00 super timer unit input timing interrupt request input timing t wcth when dfgin, cfgin, dpgin, reel0in, or reel1in logic level is input t wctl 0.8 v 0.8 v dd t wcr1h when csyncin logic level is input t wcr1l 0.8 v 0.8 v dd t wnih t wnil 0.8 v 0.8 v dd t wiph0 t wipl0 0.8 v 0.8 v dd 0.8 v 0.8 v dd 0.8 v 0.8 v dd t wiph1 t wipl1 t wiph2 t wipl2 nmi intp0, intp3 intp1, key0-key4 intp2
m pd784927, 784928, 784927y, 784928y 84 data sheet u12255ej2v0ds00 reset input timing clock output timing 0.8 v t wrsl reset t clh t cll 0.8 v 0.8 v dd clo t cycl t clf t clr
m pd784927, 784928, 784927y, 784928y 85 data sheet u12255ej2v0ds00 7. package drawing remark the package dimensions and materials of es versions are the same as those of mass-production versions. 100 pin plastic lqfp (fine pitch) (14 14) item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. s100gc-50-8eu f 1.00 0.039 b 14.00?.20 0.551 +0.009 ?.008 s 1.60 max. 0.063 max. l 0.50?.20 0.020 +0.008 ?.009 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 16.00?.20 0.630?.008 g 1.00 0.039 h 0.22 0.009?.002 i 0.08 0.003 j 0.50 (t.p.) 0.020 (t.p.) k 1.00?.20 0.039 +0.009 ?.008 n 0.08 0.003 p 1.40?.05 0.055?.002 r3 3 +7 ? +7 ? d 16.00?.20 0.630?.008 m q r k m l j h i f g p n detail of lead end m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 q 0.10?.05 0.004?.002 +0.05 ?.04 1 25 26 50 100 76 75 51 cd s a b
m pd784927, 784928, 784927y, 784928y 86 data sheet u12255ej2v0ds00 remark the package dimensions and materials of es versions are the same as those of mass-production versions. 100pin plastic qfp (14x20) item millimeters inches note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p100gf-65-3ba1-3 b 20.0?.2 0.795 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.6?.4 0.693?.016 f 0.8 0.031 g 0.6 0.024 h 0.30?.10 0.012 i 0.15 0.006 j 0.65 (t.p.) 0.026 (t.p.) k 1.8?.2 0.071 +0.008 ?.009 l 0.8?.2 0.031 n 0.10 0.004 q 0.1?.1 0.004?.004 s 3.0 max. 0.119 max. detail of lead end r q j k m l n p g f h i m p 2.7?.1 0.106 +0.005 ?.004 80 81 50 100 1 31 30 51 b a cd s a 23.6?.4 0.929?.016 m 0.15 0.006 +0.10 ?.05 r5 ? 5 ? +0.004 ?.005 +0.009 ?.008 +0.004 ?.003
m pd784927, 784928, 784927y, 784928y 87 data sheet u12255ej2v0ds00 8. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, consult nec. caution m pd784927gc- -8eu, 784927ygc- -8eu, 784928gc- -8eu, and 784928ygc- -8eu are under development. therefore their soldering conditions are not defined. table 8-1. surface mount type soldering conditions m pd784927gf- -3ba : 100-pin plastic qfp (14 20 mm) m pd784928gf- -3ba : 100-pin plastic qfp (14 20 mm) m pd784927ygf- -3ba: 100-pin plastic qfp (14 20 mm) m pd784928ygf- -3ba: 100-pin plastic qfp (14 20 mm) soldering method soldering conditions recommended conditions symbol infrared reflow package peak temperature: 235 c, time: 30 secs. max. (210 c min.), ir35-00-3 number of times: three times max. vps package peak temperature: 215 c, time: 40 secs. max. (200 c min.), vp15-00-3 number of times: three times max. wave soldering solder bath temperature: 260 c max., time: 10 secs. max., ws60-00-1 number of times: once, preheating temperature: 120 c max.(package surface temperature) partial heating pin temperature: 300 c max., time: three secs. max. (per device side) caution do not use two or more soldering methods in combination (except partial heating).
m pd784927, 784928, 784927y, 784928y 88 data sheet u12255ej2v0ds00 appendix a. development tools the following development tools are available for developing systems using the m pd784927. refer to (5) cautions when the development tools are used. (1) language processing software ra78k4 78k/iv series common assembler package cc78k4 78k/iv series common c compiler package df784928 device file for the m pd784928, 784928y subseries cc78k4-l 78k/iv series common c compiler library source file (2) flash memory writing tools flashpro ii, iii dedicated flash programmer (part number: fl-pr2, fl-pr3, pg-fpiii) fa-100gc adapter for writing 100-pin plastic lqfp (gc-8eu type) flash memory. be sure to connect depending on the target product. fa-100gf adapter for writing 100-pin plastic qfp (gf-3ba type) flash memory. be sure to connect depending on the target product. ( 3) debugging tools ? when using the ie-78k4-ns in-circuit emulator ie-78k4-ns 78k/iv series common in-circuit emulator ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c interface adapter necessary when a pc-9800 series computer (except notebook personal computer) is used as host machine (c bus compatible) ie-70000-cd-if-a pc card and interface cable necessary when a notebook personal computer is used as host machine (pcmcia socket compatible) ie-70000-pc-if-c interface adapter necessary when an ibm pc/at tm compatible machine is used as host machine (isa bus compatible) ie-784928-ns-em1 emulation board for emulating the m pd784928, 784928y subseries ep-784915-gf-r emulation probe for m pd784915 subseries common 100-pin plastic qfp (gc-3ba type) and 100-pin plastic lqfp (gc-8eu type). ev-9200gf-100 conversion socket to be mounted on the board of the target system for 100-pin plastic qfp (gf-3ba type). it is used in lcc system. nqpack100rb conversion socket to be mounted on the board of the target system for 100-pin plastic qfp (gf-3ba type). it is used in qfp system. id78k4-ns integrated debugger for ie-78k4-ns sm78k4 78k/iv series common system simulator df784928 device file for the m pd784928, 784928y subseries
m pd784927, 784928, 784927y, 784928y 89 data sheet u12255ej2v0ds00 ? when using the ie-784000-r in-circuit emulator ie-784000-r 78k/iv series common in-circuit emulator ie-70000-98-if-c interface adapter necessary when a pc-9800 series computer (except notebook personal computer) is used as host machine (c bus compatible) ie-70000-pc-if-c interface adapter necessary when an ibm pc/at compatible machine is used as host machine (isa bus compatible) ie-78000-r-sv3 interface adapter and cable necessary when an ews is used as host machine ie-784928-ns-em1 emulation board for emulating the m pd784928, 784928y subseries and m pd784915 ie-784915-r-em1 subseries ie-784000-r-em 78k/iv series common emulation board ie-78k4-r-ex3 conversion board for 100-pin products necessary when the ie-784928-ns-em1 is used in the ie-784000-r. not necessary when the ie-784915-r-em1 is used. ep-784915-gf-r emulation probe for m pd784915 subseries common 100-pin plastic qfp (gc-3ba type) and 100-pin plastic lqfp (gc-8eu type). ev-9200gf-100 conversion socket to be mounted on the board of the target system for 100-pin plastic qfp (gf-3ba type). it is used in lcc system. nqpack100rb conversion socket to be mounted on the board of the target system for 100-pin plastic qfp (gf-3ba type). it is used in qfp system. id78k4 integrated debugger for ie-784000-r sm78k4 78k/iv series common system simulator df784928 device file for the m pd784928, 784928y subseries (4) real-time os rx78k/iv real-time os for 78k/iv series mx78k4 os for 78k/iv series
m pd784927, 784928, 784927y, 784928y 90 data sheet u12255ej2v0ds00 (5) cautions when the development tools are used ? the id78k4-ns, id78k4, and sm78k4 are used in combination with the df784928. ? the cc78k4 and rx78k/iv are used in combination with the ra78k4 and df784928. ? fl-pr2, fl-pr3, fa-100gc, and fa-100gf are products of naito densei machida mfg. co., ltd. (tel: 044- 822-3813). contact an nec distributor when purchasing these products. ? nqpack100rb is a product of tokyo eletech corp. reference: daimaru kogyo, ltd. electronics dept. (tel: tokyo 03-3820-7112) electronics 2nd dept. (tel: osaka 06-6244-6672) ? host machines and oss compatible with the software are as follows: host machine [os] pc ews pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at compatible machines sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k4 note cc78k4 note id78k4-ns C id78k4 sm78k4 C rx78k/iv note mx78k4 note note dos based software
m pd784927, 784928, 784927y, 784928y 91 data sheet u12255ej2v0ds00 appendix b. related documents device-related documents document document no. japanese english m pd784928, 784928y subseries users manual - hardware u12648j u12648e m pd784927, 784928, 784927y, 784928y data sheet u12255j this document m pd784928 subseries special function register table u12798j C m pd78f4928 preliminary product information u12188j u12188e m pd784928y subseries special function register table u12719j C m pd78f4928y preliminary product information u12271j u12271e m pd784915, 784928, 784928y subseries application note - vcr servo u11361j u11361e 78k/iv series users manual - instruction u10905j u10905e 78k/iv series instruction table u10594j C 78k/iv series instruction set u10595j C 78k/iv series application note - software basics u10095j u10095e development tool-related documents (users manuals) document document no. japanese english ra78k4 assembler package operation u11334j u11334e language u11162j u11162e ra78k4 structured assembler preprocessor u11743j u11743e cc78k4 c compiler operation u11572j u11572e language u11571j u11571e ie-78k4-ns u13356j u13356e ie-784000-r u12903j eeu-1534 ie-784928-ns-em1 u13819j u13819e ie-784915-r-em1, ep-784915gf-r u10931j u10931e sm78k4 system simulator windows based reference u10093j u10093e sm78k series system simulator external part user open u10092j u10092e interface specifications id78k4-ns integrated debugger reference u12796j u12796e id78k4 integrated debugger windows based reference u10440j u10440e id78k4 integrated debugger reference u11960j u11960e hp-ux, sunos, news-os based caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of the document when designing your system.
m pd784927, 784928, 784927y, 784928y 92 data sheet u12255ej2v0ds00 embedded software-related documents (users manual) document document no. japanese english 78k/iv series real-time os fundamental u10603j u10603e installation u10604j u10604e debugger u10364j C 78k/iv series os, mx78k4 fundamental u11779j C other documents document document no. japanese english semiconductors selection guide products & packages (cd-rom) x13769x semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor devices c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by c11892j c11892e electrostatic discharge (esd) guide to microcomputer-related products by third party u11416j C caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of the document when designing your system.
m pd784927, 784928, 784927y, 784928y 93 data sheet u12255ej2v0ds00 [memo]
m pd784927, 784928, 784927y, 784928y 94 data sheet u12255ej2v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and trans- ported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. eeprom and fip are trademarks of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and new-os are trademarks of sony corporation.
m pd784927, 784928, 784927y, 784928y 95 data sheet u12255ej2v0ds00 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j99.1
m pd784927, 784928, 784927y, 784928y the documents referred to in this publication may include preliminary versions. however, preliminary versions are not marked as such. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98.8 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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